Lines Matching refs:state
242 struct radv_meta_state *state = &device->meta_state;
244 radv_DestroyPipeline(radv_device_to_handle(device), state->clear_htile_mask_pipeline,
245 &state->alloc);
246 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_htile_mask_p_layout,
247 &state->alloc);
249 radv_device_to_handle(device), state->clear_htile_mask_ds_layout, &state->alloc);
255 struct radv_meta_state *state = &device->meta_state;
259 state->clear_dcc_comp_to_single_pipeline[i], &state->alloc);
261 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_dcc_comp_to_single_p_layout,
262 &state->alloc);
264 radv_device_to_handle(device), state->clear_dcc_comp_to_single_ds_layout, &state->alloc);
270 struct radv_meta_state *state = &device->meta_state;
272 for (uint32_t i = 0; i < ARRAY_SIZE(state->color_clear); ++i) {
273 for (uint32_t j = 0; j < ARRAY_SIZE(state->color_clear[0]); ++j) {
274 for (uint32_t k = 0; k < ARRAY_SIZE(state->color_clear[i][j].color_pipelines); ++k) {
276 state->color_clear[i][j].color_pipelines[k], &state->alloc);
280 for (uint32_t i = 0; i < ARRAY_SIZE(state->ds_clear); ++i) {
283 state->ds_clear[i].depth_only_pipeline[j], &state->alloc);
285 state->ds_clear[i].stencil_only_pipeline[j], &state->alloc);
287 state->ds_clear[i].depthstencil_pipeline[j], &state->alloc);
290 state->ds_clear[i].depth_only_unrestricted_pipeline[j],
291 &state->alloc);
293 state->ds_clear[i].stencil_only_unrestricted_pipeline[j],
294 &state->alloc);
296 state->ds_clear[i].depthstencil_unrestricted_pipeline[j],
297 &state->alloc);
300 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_color_p_layout,
301 &state->alloc);
302 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_depth_p_layout,
303 &state->alloc);
305 state->clear_depth_unrestricted_p_layout, &state->alloc);
316 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
320 cmd_buffer->state.attachments ? cmd_buffer->state.attachments[pass_att].iview : NULL;
336 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
337 format = cmd_buffer->state.pass->attachments[pass_att].format;
590 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
595 cmd_buffer->state.attachments ? cmd_buffer->state.attachments[pass_att].iview : NULL;
606 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
626 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
682 struct radv_meta_state *state = &device->meta_state;
694 state->clear_htile_mask_pipeline);
697 cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->clear_htile_mask_p_layout, 0, /* set */
714 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->clear_htile_mask_p_layout,
877 cmd_buffer->state.flush_bits |= bits & ~*pre_flush;
878 *pre_flush |= cmd_buffer->state.flush_bits;
898 cmd_buffer->state.flush_bits |= flush_bits;
936 struct radv_meta_state *state = &device->meta_state;
953 &state->alloc, &state->clear_htile_mask_ds_layout);
960 .pSetLayouts = &state->clear_htile_mask_ds_layout,
970 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
971 &state->clear_htile_mask_p_layout);
987 .layout = state->clear_htile_mask_p_layout,
991 radv_pipeline_cache_to_handle(&state->cache), 1,
992 &pipeline_info, NULL, &state->clear_htile_mask_pipeline);
1051 struct radv_meta_state *state = &device->meta_state;
1067 .layout = state->clear_dcc_comp_to_single_p_layout,
1071 radv_pipeline_cache_to_handle(&state->cache), 1,
1081 struct radv_meta_state *state = &device->meta_state;
1097 &state->alloc, &state->clear_dcc_comp_to_single_ds_layout);
1104 .pSetLayouts = &state->clear_dcc_comp_to_single_ds_layout,
1114 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
1115 &state->clear_dcc_comp_to_single_p_layout);
1121 &state->clear_dcc_comp_to_single_pipeline[i]);
1134 struct radv_meta_state *state = &device->meta_state;
1186 for (uint32_t i = 0; i < ARRAY_SIZE(state->color_clear); ++i) {
1193 assert(!state->color_clear[i][0].color_pipelines[fs_key]);
1196 &state->color_clear[i][0].color_pipelines[fs_key]);
1201 for (uint32_t i = 0; i < ARRAY_SIZE(state->ds_clear); ++i) {
1206 &state->ds_clear[i].depth_only_pipeline[j]);
1211 &state->ds_clear[i].stencil_only_pipeline[j]);
1217 &state->ds_clear[i].depthstencil_pipeline[j]);
1222 &state->ds_clear[i].depth_only_unrestricted_pipeline[j]);
1228 &state->ds_clear[i].stencil_only_unrestricted_pipeline[j]);
1234 &state->ds_clear[i].depthstencil_unrestricted_pipeline[j]);
1805 cmd_buffer->state.flush_bits |= bits & ~*pre_flush;
1806 *pre_flush |= cmd_buffer->state.flush_bits;
1869 const struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
1870 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1883 fb ? cmd_buffer->state.attachments[pass_att].iview : NULL;
1904 fb ? cmd_buffer->state.attachments[ds_att->attachment].iview : NULL;
1930 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1962 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1991 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
2049 cmd_buffer->state.flush_bits |= post_flush;
2302 cmd_buffer->state.flush_bits |= flush_bits;
2366 if (!cmd_buffer->state.subpass)
2373 * state.
2378 cmd_buffer->state.subpass->view_mask, false);
2383 cmd_buffer->state.flush_bits |= post_flush;