Lines Matching refs:device
77 create_pipeline(struct radv_device *device, uint32_t samples,
87 VkDevice device_h = radv_device_to_handle(device);
91 device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache),
173 create_color_pipeline(struct radv_device *device, uint32_t samples, uint32_t frag_output,
180 mtx_lock(&device->meta_state.mtx);
182 mtx_unlock(&device->meta_state.mtx);
186 build_color_shaders(device, &vs_nir, &fs_nir, frag_output);
231 create_pipeline(device, samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
232 &rendering_create_info, device->meta_state.clear_color_p_layout,
233 &extra, &device->meta_state.alloc, pipeline);
235 mtx_unlock(&device->meta_state.mtx);
240 finish_meta_clear_htile_mask_state(struct radv_device *device)
242 struct radv_meta_state *state = &device->meta_state;
244 radv_DestroyPipeline(radv_device_to_handle(device), state->clear_htile_mask_pipeline,
246 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_htile_mask_p_layout,
248 device->vk.dispatch_table.DestroyDescriptorSetLayout(
249 radv_device_to_handle(device), state->clear_htile_mask_ds_layout, &state->alloc);
253 finish_meta_clear_dcc_comp_to_single_state(struct radv_device *device)
255 struct radv_meta_state *state = &device->meta_state;
258 radv_DestroyPipeline(radv_device_to_handle(device),
261 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_dcc_comp_to_single_p_layout,
263 device->vk.dispatch_table.DestroyDescriptorSetLayout(
264 radv_device_to_handle(device), state->clear_dcc_comp_to_single_ds_layout, &state->alloc);
268 radv_device_finish_meta_clear_state(struct radv_device *device)
270 struct radv_meta_state *state = &device->meta_state;
275 radv_DestroyPipeline(radv_device_to_handle(device),
282 radv_DestroyPipeline(radv_device_to_handle(device),
284 radv_DestroyPipeline(radv_device_to_handle(device),
286 radv_DestroyPipeline(radv_device_to_handle(device),
289 radv_DestroyPipeline(radv_device_to_handle(device),
292 radv_DestroyPipeline(radv_device_to_handle(device),
295 radv_DestroyPipeline(radv_device_to_handle(device),
300 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_color_p_layout,
302 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_depth_p_layout,
304 radv_DestroyPipelineLayout(radv_device_to_handle(device),
307 finish_meta_clear_htile_mask_state(device);
308 finish_meta_clear_dcc_comp_to_single_state(device);
315 struct radv_device *device = cmd_buffer->device;
341 fs_key = radv_format_meta_fs_key(device, format);
344 if (device->meta_state.color_clear[samples_log2][clear_att->colorAttachment]
347 device, samples, clear_att->colorAttachment, radv_fs_key_format_exemplars[fs_key],
348 &device->meta_state.color_clear[samples_log2][clear_att->colorAttachment]
356 pipeline = device->meta_state.color_clear[samples_log2][clear_att->colorAttachment]
359 assert(samples_log2 < ARRAY_SIZE(device->meta_state.color_clear));
365 device->meta_state.clear_color_p_layout, VK_SHADER_STAGE_FRAGMENT_BIT, 0,
438 create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspects,
444 mtx_lock(&device->meta_state.mtx);
446 mtx_unlock(&device->meta_state.mtx);
450 build_depthstencil_shader(device, &vs_nir, &fs_nir, unrestricted);
504 create_pipeline(device, samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
505 &rendering_create_info, device->meta_state.clear_depth_p_layout, &extra,
506 &device->meta_state.alloc, pipeline);
508 mtx_unlock(&device->meta_state.mtx);
533 radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop,
548 bool unrestricted = cmd_buffer->device->vk.enabled_extensions.EXT_depth_range_unrestricted;
574 cmd_buffer->device, aspects, 1u << samples_log2, index, unrestricted, pipeline);
588 struct radv_device *device = cmd_buffer->device;
589 struct radv_meta_state *meta_state = &device->meta_state;
616 if (cmd_buffer->device->vk.enabled_extensions.EXT_depth_range_unrestricted) {
618 device->meta_state.clear_depth_unrestricted_p_layout,
622 device->meta_state.clear_depth_p_layout, VK_SHADER_STAGE_VERTEX_BIT, 0,
681 struct radv_device *device = cmd_buffer->device;
682 struct radv_meta_state *state = &device->meta_state;
691 radv_buffer_init(&dst_buffer, device, bo, size, offset);
728 radv_get_htile_fast_clear_value(const struct radv_device *device, const struct radv_image *image,
740 if (radv_image_tile_stencil_disabled(device, image)) {
767 if (radv_image_has_vrs_htile(device, image))
780 radv_get_htile_mask(const struct radv_device *device, const struct radv_image *image,
785 if (radv_image_tile_stencil_disabled(device, image)) {
820 cmd_buffer->device, iview->image, image_layout, in_render_loop,
838 if (cmd_buffer->device->vk.enabled_extensions.EXT_depth_range_unrestricted &&
869 clear_word = radv_get_htile_fast_clear_value(cmd_buffer->device, iview->image, clear_value);
934 init_meta_clear_htile_mask_state(struct radv_device *device)
936 struct radv_meta_state *state = &device->meta_state;
938 nir_shader *cs = build_clear_htile_mask_shader(device);
952 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info,
970 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
990 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1049 create_dcc_comp_to_single_pipeline(struct radv_device *device, bool is_msaa, VkPipeline *pipeline)
1051 struct radv_meta_state *state = &device->meta_state;
1053 nir_shader *cs = build_clear_dcc_comp_to_single_shader(device, is_msaa);
1070 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1079 init_meta_clear_dcc_comp_to_single_state(struct radv_device *device)
1081 struct radv_meta_state *state = &device->meta_state;
1096 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info,
1114 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
1120 result = create_dcc_comp_to_single_pipeline(device, !!i,
1131 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1134 struct radv_meta_state *state = &device->meta_state;
1143 res = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_color_create_info,
1144 &device->meta_state.alloc,
1145 &device->meta_state.clear_color_p_layout);
1156 res = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_depth_create_info,
1157 &device->meta_state.alloc,
1158 &device->meta_state.clear_depth_p_layout);
1169 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1170 &pl_depth_unrestricted_create_info, &device->meta_state.alloc,
1171 &device->meta_state.clear_depth_unrestricted_p_layout);
1175 res = init_meta_clear_htile_mask_state(device);
1179 res = init_meta_clear_dcc_comp_to_single_state(device);
1192 unsigned fs_key = radv_format_meta_fs_key(device, format);
1195 res = create_color_pipeline(device, samples, 0, format,
1205 res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, false,
1210 res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, false,
1216 device, VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, false,
1221 res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, true,
1227 create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, true,
1233 device, VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, true,
1265 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
1313 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
1318 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
1355 struct radv_device *device = cmd_buffer->device;
1387 VkPipeline pipeline = device->meta_state.clear_dcc_comp_to_single_pipeline[is_msaa];
1403 &iview, cmd_buffer->device,
1419 device->meta_state.clear_dcc_comp_to_single_p_layout, 0,
1448 device->meta_state.clear_dcc_comp_to_single_p_layout,
1470 htile_mask = radv_get_htile_mask(cmd_buffer->device, image, range->aspectMask);
1473 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10);
1535 radv_dcc_single_clear_value(const struct radv_device *device)
1537 return device->physical_device->rad_info.gfx_level >= GFX11 ? RADV_DCC_GFX11_CLEAR_SINGLE
1542 gfx8_get_fast_clear_parameters(struct radv_device *device, const struct radv_image_view *iview,
1567 if (vi_alpha_is_on_msb(device, iview->vk.format))
1640 gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_image_view *iview,
1658 if (vi_alpha_is_on_msb(device, iview->vk.format))
1719 cmd_buffer->device, iview->image, iview->vk.base_mip_level, image_layout, in_render_loop,
1750 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1751 if (!gfx11_get_fast_clear_parameters(cmd_buffer->device, iview, &clear_value,
1755 gfx8_get_fast_clear_parameters(cmd_buffer->device, iview, &clear_value, &reset_value,
1760 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1820 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1822 gfx11_get_fast_clear_parameters(cmd_buffer->device, iview, &clear_value, &reset_value);
1825 gfx8_get_fast_clear_parameters(cmd_buffer->device, iview, &clear_value, &reset_value,
1838 if (reset_value == radv_dcc_single_clear_value(cmd_buffer->device)) {
2062 radv_image_view_init(&iview, cmd_buffer->device,
2157 radv_image_view_init(&iview, cmd_buffer->device,
2231 if (cs ? !radv_is_storage_image_format_supported(cmd_buffer->device->physical_device, format)
2232 : !radv_is_colorbuffer_format_supported(cmd_buffer->device->physical_device, format,
2244 if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
2317 !radv_image_is_renderable(cmd_buffer->device, image);