Lines Matching defs:image
333 samples = iview->image->info.samples;
520 uint32_t queue_mask = radv_image_queue_family_mask(iview->image, cmd_buffer->qf,
526 if (radv_image_is_tc_compat_htile(iview->image) &&
531 if (radv_htile_enabled(iview->image, iview->vk.base_mip_level) && iview->vk.base_mip_level == 0 &&
532 iview->vk.base_array_layer == 0 && iview->vk.layer_count == iview->image->info.array_size &&
533 radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop,
535 radv_image_extent_compare(iview->image, &iview->extent))
604 samples = iview->image->info.samples;
677 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
724 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
728 radv_get_htile_fast_clear_value(const struct radv_device *device, const struct radv_image *image,
740 if (radv_image_tile_stencil_disabled(device, image)) {
767 if (radv_image_has_vrs_htile(device, image))
780 radv_get_htile_mask(const struct radv_device *device, const struct radv_image *image,
785 if (radv_image_tile_stencil_disabled(device, image)) {
820 cmd_buffer->device, iview->image, image_layout, in_render_loop,
821 radv_image_queue_family_mask(iview->image, cmd_buffer->qf,
826 clear_rect->rect.extent.width != iview->image->info.width ||
827 clear_rect->rect.extent.height != iview->image->info.height)
830 if (view_mask && (iview->image->info.array_size >= 32 ||
831 (1u << iview->image->info.array_size) - 1u != view_mask))
835 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
843 if (radv_image_is_tc_compat_htile(iview->image) &&
849 if (iview->image->info.levels > 1) {
851 if (last_level >= iview->image->planes[0].surface.num_meta_levels) {
869 clear_word = radv_get_htile_fast_clear_value(cmd_buffer->device, iview->image, clear_value);
874 iview->image) |
876 VK_ACCESS_2_SHADER_READ_BIT, iview->image);
889 flush_bits = radv_clear_htile(cmd_buffer, iview->image, &range, clear_word);
891 if (iview->image->planes[0].surface.has_stencil &&
1243 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1250 if (radv_image_has_dcc(image)) {
1252 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1259 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1262 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.cmask_offset;
1267 size = image->planes[0].surface.cmask_size;
1269 unsigned slice_size = image->planes[0].surface.cmask_slice_size;
1272 size = slice_size * radv_get_layerCount(image, range);
1275 return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
1276 radv_buffer_get_va(image->bindings[0].bo) + offset, size, value);
1280 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1283 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.fmask_offset;
1284 unsigned slice_size = image->planes[0].surface.fmask_slice_size;
1288 assert(range->baseMipLevel == 0 && radv_get_levelCount(image, range) == 1);
1291 size = slice_size * radv_get_layerCount(image, range);
1293 return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
1294 radv_buffer_get_va(image->bindings[0].bo) + offset, size, value);
1298 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1301 uint32_t level_count = radv_get_levelCount(image, range);
1302 uint32_t layer_count = radv_get_layerCount(image, range);
1305 /* Mark the image as being compressed. */
1306 radv_update_dcc_metadata(cmd_buffer, image, range, true);
1309 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset;
1315 offset += image->planes[0].surface.meta_slice_size * range->baseArrayLayer +
1316 image->planes[0].surface.u.gfx9.meta_levels[level].offset;
1317 size = image->planes[0].surface.u.gfx9.meta_levels[level].size * layer_count;
1321 size = image->planes[0].surface.meta_size;
1324 &image->planes[0].surface.u.legacy.color.dcc_level[level];
1334 size = dcc_level->dcc_slice_fast_clear_size * radv_get_layerCount(image, range);
1341 flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
1342 radv_buffer_get_va(image->bindings[0].bo) + offset,
1351 struct radv_image *image,
1356 unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk.format);
1357 unsigned layer_count = radv_get_layerCount(image, range);
1359 bool is_msaa = image->info.samples > 1;
1392 for (uint32_t l = 0; l < radv_get_levelCount(image, range); l++) {
1396 if (!radv_dcc_enabled(image, range->baseMipLevel + l))
1399 width = radv_minify(image->info.width, range->baseMipLevel + l);
1400 height = radv_minify(image->info.height, range->baseMipLevel + l);
1406 .image = radv_image_to_handle(image),
1436 DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
1438 DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
1441 image->planes[0].surface.u.gfx9.color.dcc_block_width,
1442 image->planes[0].surface.u.gfx9.color.dcc_block_height,
1459 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
1463 radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
1466 uint32_t level_count = radv_get_levelCount(image, range);
1470 htile_mask = radv_get_htile_mask(cmd_buffer->device, image, range->aspectMask);
1472 if (level_count != image->info.levels) {
1478 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset +
1479 image->planes[0].surface.u.gfx9.meta_levels[level].offset;
1480 uint32_t size = image->planes[0].surface.u.gfx9.meta_levels[level].size;
1488 flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
1489 radv_buffer_get_va(image->bindings[0].bo) + offset,
1494 clear_htile_mask(cmd_buffer, image, image->bindings[0].bo, offset, size, value, htile_mask);
1498 unsigned layer_count = radv_get_layerCount(image, range);
1499 uint64_t size = image->planes[0].surface.meta_slice_size * layer_count;
1500 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset +
1501 image->planes[0].surface.meta_slice_size * range->baseArrayLayer;
1505 flush_bits = radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
1506 radv_buffer_get_va(image->bindings[0].bo) + offset,
1511 clear_htile_mask(cmd_buffer, image, image->bindings[0].bo, offset, size, value, htile_mask);
1554 if (iview->image->support_comp_to_single) {
1621 if ((main_value || extra_value) && iview->image->dcc_sign_reinterpret)
1699 else if (iview->image->support_comp_to_single)
1719 cmd_buffer->device, iview->image, iview->vk.base_mip_level, image_layout, in_render_loop,
1720 radv_image_queue_family_mask(iview->image, cmd_buffer->qf,
1725 clear_rect->rect.extent.width != iview->image->info.width ||
1726 clear_rect->rect.extent.height != iview->image->info.height)
1729 if (view_mask && (iview->image->info.array_size >= 32 ||
1730 (1u << iview->image->info.array_size) - 1u != view_mask))
1734 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1742 if (!iview->image->support_comp_to_single &&
1743 !radv_image_has_clear_value(iview->image) && (clear_color[0] != 0 || clear_color[1] != 0))
1746 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) {
1759 if (iview->image->info.levels > 1) {
1762 if (last_level >= iview->image->planes[0].surface.num_meta_levels) {
1770 &iview->image->planes[0].surface.u.legacy.color.dcc_level[level];
1803 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, iview->image) |
1804 radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, iview->image);
1812 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1816 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) {
1829 if (radv_image_has_cmask(iview->image)) {
1830 flush_bits = radv_clear_cmask(cmd_buffer, iview->image, &range, cmask_clear_value);
1836 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, &range, reset_value);
1839 /* Write the clear color to the first byte of each 256B block when the image supports DCC
1842 flush_bits |= radv_clear_dcc_comp_to_single(cmd_buffer, iview->image, &range, clear_color);
1845 flush_bits = radv_clear_cmask(cmd_buffer, iview->image, &range, cmask_clear_value);
1856 radv_update_fce_metadata(cmd_buffer, iview->image, &range, need_decompress_pass);
2053 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2059 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
2060 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
2065 .image = radv_image_to_handle(image),
2066 .viewType = radv_meta_get_view_type(image),
2150 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, VkFormat format,
2160 .image = radv_image_to_handle(image),
2161 .viewType = radv_meta_get_view_type(image),
2162 .format = image->vk.format,
2180 radv_minify(image->info.width, range->baseMipLevel),
2181 radv_minify(image->info.height, range->baseMipLevel),
2215 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2219 VkFormat format = image->vk.format;
2237 uint32_t queue_mask = radv_image_queue_family_mask(image, cmd_buffer->qf,
2243 /* Don't use compressed image stores because they will use an incompatible format. */
2244 if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
2267 if (!cs && radv_fast_clear_range(cmd_buffer, image, format, image_layout, false, range,
2272 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
2273 const uint32_t layer_count = image->vk.image_type == VK_IMAGE_TYPE_3D
2274 ? radv_minify(image->info.depth, range->baseMipLevel + l)
2275 : radv_get_layerCount(image, range);
2281 surf.image = image;
2290 radv_clear_image_layer(cmd_buffer, image, image_layout, range, format, l, layer_count,
2299 if (radv_dcc_enabled(image, ranges[i].baseMipLevel))
2300 flush_bits |= radv_clear_dcc(cmd_buffer, image, &ranges[i], 0xffffffffu);
2312 RADV_FROM_HANDLE(radv_image, image, image_h);
2317 !radv_image_is_renderable(cmd_buffer->device, image);
2329 radv_cmd_clear_image(cmd_buffer, image, imageLayout, (const VkClearValue *)pColor, rangeCount,
2342 RADV_FROM_HANDLE(radv_image, image, image_h);
2350 radv_cmd_clear_image(cmd_buffer, image, imageLayout, (const VkClearValue *)pDepthStencil,