Lines Matching refs:device

71 radv_device_init_meta_buffer_state(struct radv_device *device)
74    nir_shader *fill_cs = build_buffer_fill_shader(device);
75    nir_shader *copy_cs = build_buffer_copy_shader(device);
85    result = radv_CreatePipelineLayout(radv_device_to_handle(device), &fill_pl_create_info,
86                                       &device->meta_state.alloc,
87                                       &device->meta_state.buffer.fill_p_layout);
99    result = radv_CreatePipelineLayout(radv_device_to_handle(device), &copy_pl_create_info,
100                                       &device->meta_state.alloc,
101                                       &device->meta_state.buffer.copy_p_layout);
117       .layout = device->meta_state.buffer.fill_p_layout,
121       radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
122       &fill_vk_pipeline_info, NULL, &device->meta_state.buffer.fill_pipeline);
138       .layout = device->meta_state.buffer.copy_p_layout,
142       radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
143       &copy_vk_pipeline_info, NULL, &device->meta_state.buffer.copy_pipeline);
157 radv_device_finish_meta_buffer_state(struct radv_device *device)
159    struct radv_meta_state *state = &device->meta_state;
161    radv_DestroyPipeline(radv_device_to_handle(device), state->buffer.copy_pipeline, &state->alloc);
162    radv_DestroyPipeline(radv_device_to_handle(device), state->buffer.fill_pipeline, &state->alloc);
163    radv_DestroyPipelineLayout(radv_device_to_handle(device), state->buffer.copy_p_layout,
165    radv_DestroyPipelineLayout(radv_device_to_handle(device), state->buffer.fill_p_layout,
172    struct radv_device *device = cmd_buffer->device;
180                         device->meta_state.buffer.fill_pipeline);
191                          device->meta_state.buffer.fill_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0,
203    struct radv_device *device = cmd_buffer->device;
211                         device->meta_state.buffer.copy_pipeline);
222                          device->meta_state.buffer.copy_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0,
231 radv_prefer_compute_dma(const struct radv_device *device, uint64_t size,
236    if (device->physical_device->rad_info.gfx_level >= GFX10 &&
237        device->physical_device->rad_info.has_dedicated_vram) {
252    bool use_compute = radv_prefer_compute_dma(cmd_buffer->device, size, NULL, bo);
259       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo);
281                       radv_prefer_compute_dma(cmd_buffer->device, size, src_bo, dst_bo);
286    radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo);
287    radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_bo);
351    radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);
360    if (unlikely(cmd_buffer->device->trace_bo))
380       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);