Lines Matching refs:planes
99 * with no Z planes compression.
322 &image->planes[0].surface);
522 radv_patch_surface_from_metadata(device, &image->planes[plane].surface,
527 image->planes[plane].surface.flags |= RADEON_SURF_SCANOUT;
529 image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC;
536 image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC;
773 struct radv_image_plane *plane = &image->planes[plane_id];
1049 image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size) |
1066 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset;
1082 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
1090 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) |
1099 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset;
1218 if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) &&
1219 image->planes[0].surface.meta_offset) {
1244 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset;
1280 fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
1295 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode);
1297 S_008F20_PITCH(image->planes[0].surface.u.gfx9.color.fmask_epitch);
1301 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset;
1309 S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.color.fmask.tiling_index);
1312 S_008F20_PITCH(image->planes[0].surface.u.legacy.color.fmask.pitch_in_pixels - 1);
1316 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset;
1360 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0,
1361 0, image->planes[0].surface.blk_w, false, false, false, false,
1364 ac_surface_get_umd_metadata(&device->physical_device->rad_info, &image->planes[0].surface,
1372 struct radeon_surf *surface = &image->planes[0].surface;
1411 ac_surface_override_offset_stride(&device->physical_device->rad_info, &image->planes[0].surface,
1617 uint64_t flags = image->planes[i].surface.flags;
1618 uint64_t modifier = image->planes[i].surface.modifier;
1619 memset(image->planes + i, 0, sizeof(image->planes[i]));
1621 image->planes[i].surface.flags = flags;
1622 image->planes[i].surface.modifier = modifier;
1623 image->planes[i].surface.blk_w = vk_format_get_blockwidth(format);
1624 image->planes[i].surface.blk_h = vk_format_get_blockheight(format);
1625 image->planes[i].surface.bpe = vk_format_get_blocksize(format);
1628 if (image->planes[i].surface.bpe == 3) {
1629 image->planes[i].surface.bpe = 4;
1662 image->planes[plane].surface.flags |=
1666 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1670 ac_surface_zero_dcc_fields(&image->planes[0].surface);
1675 &image->planes[plane].surface, image_info.storage_samples,
1682 radv_image_alloc_single_sample_cmask(device, image, &image->planes[plane].surface);
1685 if (mod_info->pPlaneLayouts[plane].rowPitch % image->planes[plane].surface.bpe ||
1690 stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe;
1693 align64(image->size, 1 << image->planes[plane].surface.alignment_log2);
1698 &image->planes[plane].surface, image->info.levels,
1704 unsigned mem_planes = ac_surface_get_nplanes(&image->planes[plane].surface);
1710 &image->planes[plane].surface, i,
1716 image->size = MAX2(image->size, offset + image->planes[plane].surface.total_size);
1717 image->alignment = MAX2(image->alignment, 1 << image->planes[plane].surface.alignment_log2);
1719 image->planes[plane].format =
1732 assert(image->planes[0].surface.surf_size);
1733 assert(image->planes[0].surface.modifier == DRM_FORMAT_MOD_INVALID ||
1734 ac_modifier_has_dcc(image->planes[0].surface.modifier) == radv_image_has_dcc(image));
1765 const struct radv_image_plane *plane = &image->planes[i];
1888 image->planes[plane].surface.flags =
1890 image->planes[plane].surface.modifier = modifier;
1942 struct radv_image_plane *plane = &image->planes[plane_id];
2010 return image->planes[0].format;
2012 return image->planes[1].format;
2014 return image->planes[2].format;
2135 if (iview->vk.format != image->planes[iview->plane_id].format) {
2138 unsigned img_bw = vk_format_get_blockwidth(image->planes[iview->plane_id].format);
2139 unsigned img_bh = vk_format_get_blockheight(image->planes[iview->plane_id].format);
2176 iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width;
2177 iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height;
2189 iview->image->planes[0].surface.u.gfx9.base_mip_width);
2191 iview->image->planes[0].surface.u.gfx9.base_mip_height);
2410 struct radv_image_plane *plane = &image->planes[plane_id];
2471 pProperties->drmFormatModifier = image->planes[0].surface.modifier;