Lines Matching refs:metadata
411 if (md->metadata[0] != 1 || md->metadata[1] != si_get_bo_metadata_word1(device))
470 width = G_00A004_WIDTH_LO(md->metadata[3]) + (G_00A008_WIDTH_HI(md->metadata[4]) << 2) + 1;
471 height = G_00A008_HEIGHT(md->metadata[4]) + 1;
473 width = G_008F18_WIDTH(md->metadata[4]) + 1;
474 height = G_008F18_HEIGHT(md->metadata[4]) + 1;
1365 image->info.levels, desc, &md->size_metadata, md->metadata);
1370 struct radeon_bo_metadata *metadata)
1374 memset(metadata, 0, sizeof(*metadata));
1380 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode;
1381 metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8;
1382 metadata->u.gfx9.dcc_pitch_max = surface->u.gfx9.color.display_dcc_pitch_max;
1383 metadata->u.gfx9.dcc_independent_64b_blocks = surface->u.gfx9.color.dcc.independent_64B_blocks;
1384 metadata->u.gfx9.dcc_independent_128b_blocks = surface->u.gfx9.color.dcc.independent_128B_blocks;
1385 metadata->u.gfx9.dcc_max_compressed_block_size =
1387 metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1389 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D
1392 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D
1395 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1396 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1397 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1398 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1399 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1400 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1401 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1402 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1404 radv_query_opaque_metadata(device, image, metadata);
1466 /* Determine if the image is affected by the pipe misaligned metadata issue
1677 create_info.bo_metadata->metadata))