Lines Matching refs:rad_info
117 enum radeon_family family = pdevice->rad_info.family;
167 return MIN2((uint64_t)device->rad_info.vram_size_kb * 1024, (uint64_t)ov << 20);
168 return (uint64_t)device->rad_info.vram_size_kb * 1024;
174 return MIN2(radv_get_adjusted_vram_size(device), (uint64_t)device->rad_info.vram_vis_size_kb * 1024);
181 return total_size - MIN2(total_size, (uint64_t)device->rad_info.vram_vis_size_kb * 1024);
196 uint64_t gtt_size = (uint64_t)device->rad_info.gart_size_kb * 1024;
202 if (!device->rad_info.has_dedicated_vram) {
208 visible_vram_size = align64((total_size * 2) / 3, device->rad_info.gart_page_size);
291 if (device->rad_info.has_l2_uncached) {
384 return pdev->rad_info.gfx_level == GFX10_3 && !radv_thread_trace_enabled();
390 return pdevice->use_ngg && !pdevice->use_llvm && pdevice->rad_info.gfx_level >= GFX10_3 &&
392 pdevice->rad_info.has_scheduled_fence_dependency;
475 .KHR_fragment_shading_rate = device->rad_info.gfx_level >= GFX10_3,
523 .EXT_border_color_swizzle = device->rad_info.gfx_level >= GFX10,
528 .EXT_conservative_rasterization = device->rad_info.gfx_level >= GFX9,
542 .EXT_external_memory_host = device->rad_info.has_userptr,
547 .EXT_image_drm_format_modifier = device->rad_info.gfx_level >= GFX9,
550 .EXT_index_type_uint8 = device->rad_info.gfx_level >= GFX8,
563 .EXT_post_depth_coverage = device->rad_info.gfx_level >= GFX10,
570 .EXT_sample_locations = device->rad_info.gfx_level < GFX10,
572 .EXT_scalar_block_layout = device->rad_info.gfx_level >= GFX7,
589 .EXT_transform_feedback = device->rad_info.gfx_level < GFX11,
597 .AMD_gpu_shader_half_float = device->rad_info.has_packed_math_16bit,
598 .AMD_gpu_shader_int16 = device->rad_info.has_packed_math_16bit,
601 .AMD_rasterization_order = device->rad_info.has_out_of_order_rast,
606 .AMD_shader_fragment_mask = device->rad_info.gfx_level < GFX11,
619 .NV_device_generated_commands = device->rad_info.gfx_level >= GFX7 &&
637 return pdevice->rad_info.gfx_level >= GFX8;
650 if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 &&
762 device->ws->query_info(device->ws, &device->rad_info);
764 if (device->rad_info.gfx_level >= GFX11) {
786 snprintf(device->name, sizeof(device->name), "AMD RADV %s%s", device->rad_info.name,
791 marketing_name ? marketing_name : "AMD Unknown", device->rad_info.name,
812 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
815 device->rad_info.has_out_of_order_rast &&
820 device->use_ngg = (device->rad_info.gfx_level >= GFX10 &&
821 device->rad_info.family != CHIP_NAVI14 &&
823 device->rad_info.gfx_level >= GFX11;
825 device->use_ngg_culling = device->use_ngg && device->rad_info.max_render_backends > 1 &&
826 (device->rad_info.gfx_level >= GFX10_3 ||
838 if (device->rad_info.gfx_level >= GFX10) {
887 ac_print_gpu_info(&device->rad_info, stdout);
892 ac_init_perfcounters(&device->rad_info, false, false, &device->ac_perfcounters);
905 ac_get_gs_table_depth(device->rad_info.gfx_level, device->rad_info.family);
907 ac_get_hs_info(&device->rad_info, &device->hs);
908 ac_get_task_info(&device->rad_info, &device->task_info);
1327 .sparseResidencyBuffer = pdevice->rad_info.family >= CHIP_POLARIS10,
1328 .sparseResidencyImage2D = pdevice->rad_info.family >= CHIP_POLARIS10,
1329 .sparseResidencyAliased = pdevice->rad_info.family >= CHIP_POLARIS10,
1346 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit;
1370 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1396 f->scalarBlockLayout = pdevice->rad_info.gfx_level >= GFX7;
1487 features->transformFeedback = pdevice->rad_info.gfx_level < GFX11;
1488 features->geometryStreams = !pdevice->use_ngg_streamout && pdevice->rad_info.gfx_level < GFX11;
1533 features->indexTypeUint8 = pdevice->rad_info.gfx_level >= GFX8;
1546 features->shaderDeviceClock = pdevice->rad_info.gfx_level >= GFX8;
1558 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1571 features->stippledBresenhamLines = pdevice->rad_info.gfx_level != GFX9;
1610 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.gfx_level >= GFX8;
1646 pdevice->rad_info.gfx_level < GFX11; /* TODO: VRS no longer uses HTILE. */
1711 pdevice->rad_info.gfx_level != GFX8 && pdevice->rad_info.gfx_level != GFX9;
1970 .maxComputeSharedMemorySize = pdevice->rad_info.gfx_level >= GFX7 ? 65536 : 32768,
2011 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
2029 if (pdevice->rad_info.has_dedicated_vram) {
2039 .deviceID = pdevice->rad_info.pci_id,
2044 .residencyNonResidentStrict = pdevice->rad_info.family >= CHIP_POLARIS10,
2045 .residencyStandard2DBlockShape = pdevice->rad_info.family >= CHIP_POLARIS10,
2095 if (pdevice->rad_info.gfx_level >= GFX10_3) {
2122 if (pdevice->rad_info.has_packed_math_16bit) {
2144 pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
2145 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
2146 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
2147 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
2148 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
2150 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.gfx_level >= GFX8 && !pdevice->use_llvm;
2151 p->shaderDenormPreserveFloat64 = pdevice->rad_info.gfx_level >= GFX8;
2152 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.gfx_level >= GFX8;
2153 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.gfx_level >= GFX8 && !pdevice->use_llvm;
2154 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.gfx_level >= GFX8;
2201 p->filterMinmaxImageComponentMapping = pdevice->rad_info.gfx_level >= GFX9;
2219 if (pdevice->rad_info.gfx_level >= GFX10) {
2232 bool accel = pdevice->rad_info.has_accelerated_dot_product;
2327 properties->shaderEngineCount = pdevice->rad_info.max_se;
2328 properties->shaderArraysPerEngineCount = pdevice->rad_info.max_sa_per_se;
2329 properties->computeUnitsPerShaderArray = pdevice->rad_info.min_good_cu_per_sa;
2330 properties->simdPerComputeUnit = pdevice->rad_info.num_simd_per_compute_unit;
2331 properties->wavefrontsPerSimd = pdevice->rad_info.max_wave64_per_simd;
2335 properties->sgprsPerSimd = pdevice->rad_info.num_physical_sgprs_per_simd;
2336 properties->minSgprAllocation = pdevice->rad_info.min_sgpr_alloc;
2337 properties->maxSgprAllocation = pdevice->rad_info.max_sgpr_alloc;
2338 properties->sgprAllocationGranularity = pdevice->rad_info.sgpr_alloc_granularity;
2341 properties->vgprsPerSimd = pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
2342 properties->minVgprAllocation = pdevice->rad_info.min_wave64_vgpr_alloc;
2343 properties->maxVgprAllocation = pdevice->rad_info.max_vgpr_alloc;
2344 properties->vgprAllocationGranularity = pdevice->rad_info.wave64_vgpr_alloc_granularity;
2352 properties->activeComputeUnitCount = pdevice->rad_info.num_cu;
2600 if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 &&
2624 if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 &&
2630 .queueCount = pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues,
2699 if (!device->rad_info.has_dedicated_vram) {
2735 device->rad_info.gart_page_size);
3531 device->pbb_allowed = device->physical_device->rad_info.gfx_level >= GFX9 &&
3548 MAX2(32 * physical_device->rad_info.num_cu, max_threads_per_block / 64);
3552 if (device->physical_device->rad_info.gfx_level >= GFX7) {
3591 if (device->physical_device->rad_info.gfx_level < GFX8 ||
3592 device->physical_device->rad_info.gfx_level > GFX10_3) {
3609 if (device->physical_device->rad_info.gfx_level >= GFX10) {
3621 assert(device->physical_device->rad_info.gfx_level == GFX8);
3636 if (device->physical_device->rad_info.gfx_level >= GFX10_3) {
3656 device->load_grid_size_from_user_sgpr = device->physical_device->rad_info.gfx_level >= GFX10_3;
3678 if (device->physical_device->rad_info.gfx_level >= GFX7)
3873 if (device->physical_device->rad_info.gfx_level >= GFX11)
3878 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3881 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
3884 } else if (device->physical_device->rad_info.gfx_level >= GFX8) {
3902 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3905 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
3928 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3931 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
3949 if (device->physical_device->rad_info.gfx_level >= GFX11)
3954 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3957 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
3960 } else if (device->physical_device->rad_info.gfx_level >= GFX8) {
3982 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3985 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
3999 if (device->physical_device->rad_info.gfx_level >= GFX11) {
4002 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
4024 if (device->physical_device->rad_info.gfx_level >= GFX11) {
4028 assert(device->physical_device->rad_info.gfx_level >= GFX10_3);
4039 if (device->physical_device->rad_info.gfx_level >= GFX11) {
4043 assert(device->physical_device->rad_info.gfx_level >= GFX10_3);
4060 if (device->physical_device->rad_info.gfx_level >= GFX11) {
4064 assert(device->physical_device->rad_info.gfx_level >= GFX10_3);
4098 if (device->physical_device->rad_info.gfx_level >= GFX7) {
4123 if (device->physical_device->rad_info.gfx_level >= GFX7) {
4124 if (device->physical_device->rad_info.gfx_level >= GFX11) {
4126 tf_ring_size /= device->physical_device->rad_info.max_se;
4132 if (device->physical_device->rad_info.gfx_level >= GFX10) {
4135 } else if (device->physical_device->rad_info.gfx_level == GFX9) {
4203 struct radeon_info *info = &device->physical_device->rad_info;
4232 struct radeon_info *info = &device->physical_device->rad_info;
4242 if (device->physical_device->rad_info.gfx_level >= GFX11)
4295 if (device->physical_device->rad_info.gfx_level >= GFX11) {
4303 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
4311 } else if (device->physical_device->rad_info.gfx_level == GFX9) {
4418 assert(device->physical_device->rad_info.gfx_level >= GFX10_3);
4438 assert(device->physical_device->rad_info.gfx_level >= GFX10_3);
4448 assert(device->physical_device->rad_info.gfx_level >= GFX10);
4460 assert(device->physical_device->rad_info.gfx_level >= GFX10);
4505 if (device->physical_device->rad_info.gfx_level >= GFX11)
4527 device->physical_device->rad_info.gfx_level >= GFX7)
4596 const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
4844 if (device->physical_device->rad_info.gfx_level >= GFX9) {
5606 device->physical_device->rad_info.max_alignment, domain,
6158 if (device->physical_device->rad_info.gfx_level < GFX10 && iview->image->info.samples > 1) {
6171 if (!device->physical_device->rad_info.has_dedicated_vram) {
6197 if (device->physical_device->rad_info.gfx_level >= GFX9) {
6227 if (device->physical_device->rad_info.gfx_level >= GFX11) {
6254 if (device->physical_device->rad_info.gfx_level >= GFX11)
6265 if (device->physical_device->rad_info.gfx_level >= GFX9) {
6266 if (device->physical_device->rad_info.gfx_level >= GFX11) {
6269 } else if (device->physical_device->rad_info.gfx_level >= GFX10) {
6311 if (device->physical_device->rad_info.gfx_level >= GFX7)
6318 if (device->physical_device->rad_info.gfx_level >= GFX7)
6334 device->physical_device->rad_info.gfx_level <= GFX8)
6351 if (device->physical_device->rad_info.gfx_level >= GFX11)
6403 if (device->physical_device->rad_info.gfx_level >= GFX11)
6410 if (device->physical_device->rad_info.gfx_level == GFX6) {
6423 if (device->physical_device->rad_info.gfx_level == GFX8) {
6437 device->physical_device->rad_info.gfx_level < GFX11)
6443 if (!radv_image_has_fmask(iview->image) && device->physical_device->rad_info.gfx_level == GFX6) {
6448 if (device->physical_device->rad_info.gfx_level >= GFX9) {
6457 if (device->physical_device->rad_info.gfx_level >= GFX10) {
6462 S_028EE0_RESOURCE_LEVEL(device->physical_device->rad_info.gfx_level >= GFX11 ? 0 : 1);
6481 if (device->physical_device->rad_info.gfx_level >= GFX9) {
6489 if (device->physical_device->rad_info.has_two_planes_iterate256_bug &&
6584 if (device->physical_device->rad_info.gfx_level >= GFX10) {
6595 if (device->physical_device->rad_info.gfx_level >= GFX9) {
6604 S_028040_ITERATE_256(device->physical_device->rad_info.gfx_level >= GFX11);
6607 S_028044_ITERATE_256(device->physical_device->rad_info.gfx_level >= GFX11);
6609 if (device->physical_device->rad_info.gfx_level == GFX9) {
6626 if (device->physical_device->rad_info.gfx_level >= GFX10) {
6648 if (device->physical_device->rad_info.gfx_level == GFX9) {
6672 if (device->physical_device->rad_info.gfx_level >= GFX7) {
6673 struct radeon_info *info = &device->physical_device->rad_info;
6902 bool compat_mode = device->physical_device->rad_info.gfx_level == GFX8 ||
6903 device->physical_device->rad_info.gfx_level == GFX9;
6965 if (device->physical_device->rad_info.gfx_level >= GFX10) {
6970 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.gfx_level <= GFX8) |
6973 device->physical_device->rad_info.gfx_level >= GFX8);
6976 if (device->physical_device->rad_info.gfx_level >= GFX11) {
7232 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7373 if (device->physical_device->rad_info.has_stable_pstate) {