Lines Matching refs:pdevice
115 radv_device_get_cache_uuid(struct radv_physical_device *pdevice, void *uuid)
117 enum radeon_family family = pdevice->rad_info.family;
137 if (pdevice->use_llvm &&
322 radv_get_compiler_string(struct radv_physical_device *pdevice)
324 if (!pdevice->use_llvm) {
329 if (driQueryOptionb(&pdevice->instance->dri_options, "radv_report_llvm9_version_string")) {
388 radv_taskmesh_enabled(const struct radv_physical_device *pdevice)
390 return pdevice->use_ngg && !pdevice->use_llvm && pdevice->rad_info.gfx_level >= GFX10_3 &&
391 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE) &&
392 pdevice->rad_info.has_scheduled_fence_dependency;
635 radv_is_conformant(const struct radv_physical_device *pdevice)
637 return pdevice->rad_info.gfx_level >= GFX8;
641 radv_physical_device_init_queue_table(struct radv_physical_device *pdevice)
644 pdevice->vk_queue_to_radv[idx] = RADV_QUEUE_GENERAL;
648 pdevice->vk_queue_to_radv[i] = RADV_MAX_QUEUE_FAMILIES + 1;
650 if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 &&
651 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
652 pdevice->vk_queue_to_radv[idx] = RADV_QUEUE_COMPUTE;
655 pdevice->num_queues = idx;
1152 list_for_each_entry_safe(struct radv_physical_device, pdevice, &instance->physical_devices, link)
1154 radv_physical_device_destroy(pdevice);
1181 struct radv_physical_device *pdevice;
1183 result = radv_physical_device_try_create(instance, NULL, &pdevice);
1187 list_addtail(&pdevice->link, &instance->physical_devices);
1207 struct radv_physical_device *pdevice;
1208 result = radv_physical_device_try_create(instance, devices[i], &pdevice);
1219 list_addtail(&pdevice->link, &instance->physical_devices);
1240 list_for_each_entry(struct radv_physical_device, pdevice, &instance->physical_devices, link)
1244 *i = radv_physical_device_to_handle(pdevice);
1263 list_for_each_entry(struct radv_physical_device, pdevice, &instance->physical_devices, link)
1269 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
1280 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1304 .textureCompressionETC2 = radv_device_supports_etc(pdevice) || pdevice->emulate_etc2,
1327 .sparseResidencyBuffer = pdevice->rad_info.family >= CHIP_POLARIS10,
1328 .sparseResidencyImage2D = pdevice->rad_info.family >= CHIP_POLARIS10,
1329 .sparseResidencyAliased = pdevice->rad_info.family >= CHIP_POLARIS10,
1338 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
1346 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit;
1358 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1370 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1396 f->scalarBlockLayout = pdevice->rad_info.gfx_level >= GFX7;
1414 radv_get_physical_device_features_1_3(struct radv_physical_device *pdevice,
1440 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1446 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1451 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1456 radv_get_physical_device_features_1_3(pdevice, &core_1_3);
1487 features->transformFeedback = pdevice->rad_info.gfx_level < GFX11;
1488 features->geometryStreams = !pdevice->use_ngg_streamout && pdevice->rad_info.gfx_level < GFX11;
1533 features->indexTypeUint8 = pdevice->rad_info.gfx_level >= GFX8;
1546 features->shaderDeviceClock = pdevice->rad_info.gfx_level >= GFX8;
1558 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1571 features->stippledBresenhamLines = pdevice->rad_info.gfx_level != GFX9;
1610 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.gfx_level >= GFX8;
1645 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_HIZ) &&
1646 pdevice->rad_info.gfx_level < GFX11; /* TODO: VRS no longer uses HTILE. */
1709 bool has_shader_buffer_float_minmax = radv_has_shader_buffer_float_minmax(pdevice);
1711 pdevice->rad_info.gfx_level != GFX8 && pdevice->rad_info.gfx_level != GFX9;
1753 features->rayTracingPipelineTraceRaysIndirect2 = radv_enable_rt(pdevice, true);
1789 features->taskShader = features->meshShader = radv_taskmesh_enabled(pdevice);
1853 features->performanceCounterQueryPools = radv_perf_query_supported(pdevice);
1893 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1896 driQueryOptioni(&pdevice->instance->dri_options, "radv_override_uniform_offset_alignment");
1913 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1970 .maxComputeSharedMemorySize = pdevice->rad_info.gfx_level >= GFX7 ? 65536 : 32768,
1987 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
2011 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
2029 if (pdevice->rad_info.has_dedicated_vram) {
2039 .deviceID = pdevice->rad_info.pci_id,
2044 .residencyNonResidentStrict = pdevice->rad_info.family >= CHIP_POLARIS10,
2045 .residencyStandard2DBlockShape = pdevice->rad_info.family >= CHIP_POLARIS10,
2049 strcpy(pProperties->deviceName, pdevice->marketing_name);
2050 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
2054 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
2059 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
2060 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
2084 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
2092 radv_get_compiler_string(pdevice));
2094 if (radv_is_conformant(pdevice)) {
2095 if (pdevice->rad_info.gfx_level >= GFX10_3) {
2122 if (pdevice->rad_info.has_packed_math_16bit) {
2138 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
2140 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
2144 pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
2145 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
2146 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
2147 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
2148 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
2150 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.gfx_level >= GFX8 && !pdevice->use_llvm;
2151 p->shaderDenormPreserveFloat64 = pdevice->rad_info.gfx_level >= GFX8;
2152 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.gfx_level >= GFX8;
2153 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.gfx_level >= GFX8 && !pdevice->use_llvm;
2154 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.gfx_level >= GFX8;
2201 p->filterMinmaxImageComponentMapping = pdevice->rad_info.gfx_level >= GFX9;
2210 radv_get_physical_device_properties_1_3(struct radv_physical_device *pdevice,
2219 if (pdevice->rad_info.gfx_level >= GFX10) {
2232 bool accel = pdevice->rad_info.has_accelerated_dot_product;
2276 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2282 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
2287 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
2292 radv_get_physical_device_properties_1_3(pdevice, &core_1_3);
2327 properties->shaderEngineCount = pdevice->rad_info.max_se;
2328 properties->shaderArraysPerEngineCount = pdevice->rad_info.max_sa_per_se;
2329 properties->computeUnitsPerShaderArray = pdevice->rad_info.min_good_cu_per_sa;
2330 properties->simdPerComputeUnit = pdevice->rad_info.num_simd_per_compute_unit;
2331 properties->wavefrontsPerSimd = pdevice->rad_info.max_wave64_per_simd;
2335 properties->sgprsPerSimd = pdevice->rad_info.num_physical_sgprs_per_simd;
2336 properties->minSgprAllocation = pdevice->rad_info.min_sgpr_alloc;
2337 properties->maxSgprAllocation = pdevice->rad_info.max_sgpr_alloc;
2338 properties->sgprAllocationGranularity = pdevice->rad_info.sgpr_alloc_granularity;
2341 properties->vgprsPerSimd = pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
2342 properties->minVgprAllocation = pdevice->rad_info.min_wave64_vgpr_alloc;
2343 properties->maxVgprAllocation = pdevice->rad_info.max_vgpr_alloc;
2344 properties->vgprAllocationGranularity = pdevice->rad_info.wave64_vgpr_alloc_granularity;
2352 properties->activeComputeUnitCount = pdevice->rad_info.num_cu;
2379 properties->pciDomain = pdevice->bus_info.domain;
2380 properties->pciBus = pdevice->bus_info.bus;
2381 properties->pciDevice = pdevice->bus_info.dev;
2382 properties->pciFunction = pdevice->bus_info.func;
2395 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
2396 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
2481 if (pdevice->available_nodes & (1 << DRM_NODE_PRIMARY)) {
2483 props->primaryMajor = (int64_t)major(pdevice->primary_devid);
2484 props->primaryMinor = (int64_t)minor(pdevice->primary_devid);
2488 if (pdevice->available_nodes & (1 << DRM_NODE_RENDER)) {
2490 props->renderMajor = (int64_t)major(pdevice->render_devid);
2491 props->renderMinor = (int64_t)minor(pdevice->render_devid);
2594 radv_get_physical_device_queue_family_properties(struct radv_physical_device *pdevice,
2600 if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 &&
2601 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2624 if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 &&
2625 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2630 .queueCount = pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues,
2651 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2653 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2661 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2792 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2794 pMemoryProperties->memoryProperties = pdevice->memory_properties;