Lines Matching defs:image
1880 * be at most 2 GiB. the combined image & samples object count as one of
1888 32 /* sampler, largest when combined with image */ + 64 /* sampled image */ +
1889 64 /* storage image */);
2170 32 /* sampler, largest when combined with image */ + 64 /* sampled image */ +
2171 64 /* storage image */);
3059 VkImage image;
3078 &device->meta_state.alloc, &image);
3084 .size = radv_image_from_handle(image)->planes[0].surface.meta_size,
3124 device->vrs.image = radv_image_from_handle(image);
3135 radv_DestroyImage(radv_device_to_handle(device), image, &device->meta_state.alloc);
3143 if (!device->vrs.image)
3150 radv_DestroyImage(radv_device_to_handle(device), radv_image_to_handle(device->vrs.image),
4797 RADV_FROM_HANDLE(radv_image, image, bind->image);
4806 result = device->ws->buffer_virtual_bind(device->ws, image->bindings[0].bo,
4819 RADV_FROM_HANDLE(radv_image, image, bind->image);
4820 struct radeon_surf *surface = &image->planes[0].surface;
4821 uint32_t bs = vk_format_get_blocksize(image->vk.format);
4833 DIV_ROUND_UP(bind_extent.width, vk_format_get_blockwidth(image->vk.format));
4835 DIV_ROUND_UP(bind_extent.height, vk_format_get_blockheight(image->vk.format));
4838 bind_offset.x /= vk_format_get_blockwidth(image->vk.format);
4839 bind_offset.y /= vk_format_get_blockheight(image->vk.format);
4863 result = device->ws->buffer_virtual_bind(device->ws, image->bindings[0].bo, offset, size,
4873 image->bindings[0].bo, offset + img_increment * y, size, mem ? mem->bo : NULL,
5376 if (memory->image && memory->image->bindings[0].offset == 0) {
5378 radv_init_metadata(device, memory->image, &metadata);
5486 mem->image = radv_image_from_handle(dedicate_info->image);
5489 mem->image = NULL;
5540 if (mem->image && mem->image->plane_count == 1 &&
5541 !vk_format_is_depth_or_stencil(mem->image->vk.format) && mem->image->info.samples == 1 &&
5542 mem->image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
5552 result = radv_image_create_layout(device, create_info, NULL, mem->image);
5781 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5787 pMemoryRequirements->memoryRequirements.size = image->size;
5788 pMemoryRequirements->memoryRequirements.alignment = image->alignment;
5796 image->shareable && image->vk.tiling != VK_IMAGE_TILING_LINEAR;
5812 VkImage image;
5814 /* Determining the image size/alignment require to create a surface, which is complicated without
5815 * creating an image.
5816 * TODO: Avoid creating an image.
5818 result = radv_CreateImage(device, pInfo->pCreateInfo, NULL, &image);
5823 .image = image,
5828 radv_DestroyImage(device, image, NULL);
5879 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5884 .image = pBindInfos[i].image,
5894 "Device memory object too small for the image.\n");
5898 if (image->disjoint) {
5904 image->bindings[0].bo = mem->bo;
5905 image->bindings[0].offset = pBindInfos[i].memoryOffset;
5908 image->bindings[1].bo = mem->bo;
5909 image->bindings[1].offset = pBindInfos[i].memoryOffset;
5912 image->bindings[2].bo = mem->bo;
5913 image->bindings[2].offset = pBindInfos[i].memoryOffset;
5919 image->bindings[0].bo = mem->bo;
5920 image->bindings[0].offset = pBindInfos[i].memoryOffset;
6158 if (device->physical_device->rad_info.gfx_level < GFX10 && iview->image->info.samples > 1) {
6159 if (iview->image->planes[0].surface.bpe == 1)
6161 else if (iview->image->planes[0].surface.bpe == 2)
6192 if (!radv_dcc_enabled(iview->image, iview->vk.base_mip_level))
6199 iview->image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size;
6200 independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks;
6201 independent_64b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks;
6205 if (iview->image->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6207 /* If this DCC image is potentially going to be used in texture
6230 S_028C78_FDCC_ENABLE(radv_dcc_enabled(iview->image, iview->vk.base_mip_level));
6246 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6259 uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0;
6260 va = radv_buffer_get_va(iview->image->bindings[plane_id].bo) +
6261 iview->image->bindings[plane_id].offset;
6310 if (radv_image_has_fmask(iview->image)) {
6326 va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset;
6330 va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset;
6333 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) &&
6348 if (iview->image->info.samples > 1) {
6349 unsigned log_samples = util_logbase2(iview->image->info.samples);
6358 if (radv_image_has_fmask(iview->image)) {
6359 va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset +
6408 if (radv_image_has_fmask(iview->image)) {
6415 if (radv_image_is_tc_compat_cmask(iview->image)) {
6432 if (radv_image_has_cmask(iview->image) &&
6436 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && !iview->disable_dcc_mrt &&
6443 if (!radv_image_has_fmask(iview->image) && device->physical_device->rad_info.gfx_level == GFX6) {
6449 unsigned mip0_depth = iview->image->vk.image_type == VK_IMAGE_TYPE_3D
6451 : (iview->image->info.array_size - 1);
6453 vk_format_get_plane_width(iview->image->vk.format, iview->plane_id, iview->extent.width);
6455 vk_format_get_plane_height(iview->image->vk.format, iview->plane_id, iview->extent.height);
6470 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6479 assert(radv_image_is_tc_compat_htile(iview->image));
6485 if (iview->vk.format == VK_FORMAT_D16_UNORM && iview->image->info.samples > 1)
6490 radv_image_get_iterate256(device, iview->image) &&
6491 !radv_image_tile_stencil_disabled(device, iview->image) &&
6492 iview->image->info.samples == 4) {
6507 if (iview->image->info.samples <= 1)
6509 else if (iview->image->info.samples <= 4)
6520 radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer,
6523 const struct radeon_surf *surf = &image->planes[0].surface;
6525 assert(image->vk.format == VK_FORMAT_D16_UNORM);
6536 ds->db_depth_size = S_02801C_X_MAX(image->info.width - 1) |
6537 S_02801C_Y_MAX(image->info.height - 1);
6551 bool stencil_only = iview->image->vk.format == VK_FORMAT_S8_UINT;
6552 const struct radv_image_plane *plane = &iview->image->planes[0];
6555 assert(vk_format_get_plane_count(iview->image->vk.format) == 1);
6559 switch (iview->image->vk.format) {
6578 format = radv_translate_dbformat(iview->image->vk.format);
6592 va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset;
6600 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6602 S_028038_MAXMIP(iview->image->info.levels - 1) |
6615 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6616 S_02801C_Y_MAX(iview->image->info.height - 1);
6618 if (radv_htile_enabled(iview->image, level)) {
6621 if (radv_image_is_tc_compat_htile(iview->image)) {
6627 bool iterate256 = radv_image_get_iterate256(device, iview->image);
6639 if (radv_image_tile_stencil_disabled(device, iview->image)) {
6643 va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset +
6652 if (radv_image_has_vrs_htile(device, iview->image)) {
6665 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6669 if (iview->image->info.samples > 1)
6670 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6693 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6695 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6706 if (radv_htile_enabled(iview->image, level)) {
6709 if (radv_image_tile_stencil_disabled(device, iview->image)) {
6713 va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset +
6718 if (radv_image_is_tc_compat_htile(iview->image)) {