Lines Matching refs:radeon_emit
48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
56 radeon_emit(cs, value);
65 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
66 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
73 radeon_emit(cs, value);
81 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
82 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
83 radeon_emit(cs, value);
91 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
92 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
93 radeon_emit(cs, mask);
94 radeon_emit(cs, value);
103 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
104 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
111 radeon_emit(cs, value);
126 radeon_emit(cs, PKT3(opcode, 1, 0));
127 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
128 radeon_emit(cs, value);
137 radeon_emit(cs, PKT3(PKT3_SET_SH_REG_INDEX, 1, 0));
138 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (3 << 28));
139 radeon_emit(cs, value);
148 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
149 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
158 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));
159 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
166 radeon_emit(cs, value);
182 radeon_emit(cs, PKT3(opcode, 1, 0));
183 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
184 radeon_emit(cs, value);
202 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0) | PKT3_RESET_FILTER_CAM(filter_cam_workaround));
203 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
204 radeon_emit(cs, value);
213 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
214 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF));
215 radeon_emit(cs, value);
216 radeon_emit(cs, 0); /* unused */
217 radeon_emit(cs, reg >> 2);
218 radeon_emit(cs, 0); /* unused */