Lines Matching refs:depth
2249 * Update the fast clear depth/stencil values if the image is bound as a
2250 * depth/stencil buffer.
2275 radeon_emit(cs, fui(ds_clear_value.depth));
2277 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(ds_clear_value.depth));
2286 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && ds_clear_value.depth == 0.0) {
2298 * Set the clear depth/stencil values to the image's metadata.
2319 radeon_emit(cs, fui(ds_clear_value.depth));
2328 value = fui(ds_clear_value.depth);
2384 * depth clear value is 0.0f.
2386 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
2392 * Update the clear depth/stencil values for this image.
2420 * Load the clear depth/stencil values from the image's metadata.
2815 /* Only load the depth/stencil fast clear values when
2821 /* When a subpass uses a VRS attachment without binding a depth/stencil attachment, we have to
2822 * bind our internal depth buffer that contains the VRS data as part of HTILE.
2858 * VRS and occlusion queries if depth and stencil are not bound.
2954 * covered tiles, discards, and early depth testing. For more details,
4618 * performed a fast color/depth clear to the whole image
4632 /* Determine if the subpass uses separate depth/stencil layouts. */
4640 /* For separate layouts, perform depth and stencil transitions
6199 * fast color/depth clears can't work.
6406 /* When a subpass uses a VRS attachment and a depth/stencil attachment, we just need to
6432 /* When a subpass uses a VRS attachment without binding a depth/stencil attachment, we have
8749 info.blocks[2] = tables->depth;
8776 uint32_t width, uint32_t height, uint32_t depth)
8794 .depth = depth,
8994 clear_values[att_count].depthStencil.depth =
8995 pRenderingInfo->pDepthAttachment->clearValue.depthStencil.depth;
9216 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
9217 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
9218 * 0xfffffff0: Clear depth to 1.0
9219 * 0x00000000: Clear depth to 0.0
9254 * a fast depth clear.