Lines Matching refs:base
432 vk_object_base_finish(&set->base);
435 vk_object_base_finish(&cmd_buffer->meta_push_descriptors.base);
473 vk_object_base_init(&device->vk, &cmd_buffer->meta_push_descriptors.base,
479 vk_object_base_init(&device->vk, &cmd_buffer->descriptors[i].push_set.set.base,
1228 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
1245 if (pipeline->base.device->physical_device->rad_info.gfx_level < GFX9)
1295 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_VERTEX]);
1298 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_MESH]);
1304 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_TESS_CTRL]);
1307 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_TESS_EVAL]);
1310 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_GEOMETRY]);
1311 if (radv_pipeline_has_gs_copy_shader(&pipeline->base))
1312 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.gs_copy_shader);
1316 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_FRAGMENT]);
1497 cmd_buffer->state.emitted_graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT] !=
1498 cmd_buffer->state.graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]) &&
1523 MAX2(cmd_buffer->scratch_size_per_wave_needed, pipeline->base.scratch_bytes_per_wave);
1524 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, pipeline->base.max_waves);
1571 radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
1580 struct radv_shader *v = pipeline->base.shaders[pipeline->last_vgt_api_stage];
1587 cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs.cdw != pipeline->base.ctx_cs.cdw ||
1588 cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs_hash != pipeline->base.ctx_cs_hash ||
1589 memcmp(cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs.buf, pipeline->base.ctx_cs.buf,
1590 pipeline->base.ctx_cs.cdw * 4)) {
1591 radeon_emit_array(cmd_buffer->cs, pipeline->base.ctx_cs.buf, pipeline->base.ctx_cs.cdw);
1597 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.slab_bo);
1600 radv_save_pipeline(cmd_buffer, &pipeline->base);
3232 if (vs_shader->info.is_ngg || pipeline->base.shaders[MESA_SHADER_GEOMETRY] == vs_shader) {
3235 } else if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL] == vs_shader) {
3299 uint32_t base_reg = cmd_buffer->state.graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX];
3310 struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX);
3517 if (!cmd_buffer->state.graphics_pipeline->base.shaders[stage])
3561 const uint8_t base = ffs(mask) - 1;
3562 if (mask == u_bit_consecutive64(base, util_last_bit64(mask) - base)) {
3565 values + base);
3703 struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX);
3873 radv_emit_userdata_address(cmd_buffer->device, cmd_buffer->cs, &pipeline->base,
3893 if (!radv_get_shader(&pipeline->base, stage))
3896 loc = radv_lookup_user_sgpr(&pipeline->base, stage, AC_UD_STREAMOUT_BUFFERS);
3900 base_reg = pipeline->base.user_data_0[stage];
3906 if (radv_pipeline_has_gs_copy_shader(&pipeline->base)) {
3907 loc = &pipeline->base.gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
3995 loc = radv_lookup_user_sgpr(&pipeline->base, stage, AC_UD_NGG_QUERY_STATE);
4010 base_reg = pipeline->base.user_data_0[stage];
4020 enum amd_gfx_level gfx_level = pipeline->base.device->physical_device->rad_info.gfx_level;
4032 loc = radv_lookup_user_sgpr(&pipeline->base, stage, AC_UD_FORCE_VRS_RATES);
4035 base_reg = pipeline->base.user_data_0[stage];
4069 radv_flush_descriptors(cmd_buffer, stages, &pipeline->base, VK_PIPELINE_BIND_POINT_GRAPHICS);
4070 radv_flush_constants(cmd_buffer, stages, &pipeline->base, VK_PIPELINE_BIND_POINT_GRAPHICS);
5495 assert(!pipeline->base.ctx_cs.cdw);
5499 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.cs.cdw);
5500 radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
5503 MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, pipeline->base.scratch_bytes_per_wave);
5505 MAX2(cmd_buffer->compute_scratch_waves_wanted, pipeline->base.max_waves);
5507 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.slab_bo);
5510 radv_save_pipeline(cmd_buffer, &pipeline->base);
6561 struct radv_userdata_info *loc = radv_lookup_user_sgpr(&pipeline->base, stage, AC_UD_VIEW_INDEX);
6564 uint32_t base_reg = pipeline->base.user_data_0[stage];
6576 if (radv_pipeline_has_gs_copy_shader(&pipeline->base)) {
6578 &pipeline->base.gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
6736 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6766 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6815 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6932 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6953 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
7509 const struct radv_shader *v = pipeline->base.shaders[stage];
7513 const uint32_t base_reg = pipeline->base.user_data_0[stage];
7748 struct radv_shader *task_shader = radv_get_shader(&pipeline->base, MESA_SHADER_TASK);
7787 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_TASK_BIT_NV, &pipeline->base,
7789 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_TASK_BIT_NV, &pipeline->base,
8407 struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
8416 loc = radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
8560 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT, &pipeline->base, bind_point);
8565 &pipeline->base, bind_point);
8603 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_COMPUTE]);
8612 radv_emit_shader_prefetch(cmd_buffer, pipeline->base.shaders[MESA_SHADER_COMPUTE]);
8718 uint32_t base_reg = pipeline->base.user_data_0[MESA_SHADER_COMPUTE];
8754 radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_COMPUTE, AC_UD_CS_SBT_DESCRIPTORS);
8761 radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_COMPUTE, AC_UD_CS_RAY_LAUNCH_SIZE_ADDR);
8846 scratch_bytes_per_wave = cmd_buffer->state.rt_pipeline->base.scratch_bytes_per_wave;
8847 wave_size = cmd_buffer->state.rt_pipeline->base.shaders[MESA_SHADER_COMPUTE]->info.wave_size;