Lines Matching defs:value
772 /* GFX writes a value to the semaphore which ACE can wait for.*/
1386 /* Disable value checking for disabled channels. */
2136 /* When we don't know the last fast clear value we need to emit a
2241 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
2283 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
2325 unsigned value;
2328 value = fui(ds_clear_value.depth);
2332 value = ds_clear_value.stencil;
2340 radeon_emit(cs, value);
2346 * Update the TC-compat metadata value for this image.
2350 const VkImageSubresourceRange *range, uint32_t value)
2366 radeon_emit(cs, value);
2384 * depth clear value is 0.0f.
2466 * used as a texture. This sets a predicate value to determine if the
2471 const VkImageSubresourceRange *range, bool value)
2476 uint64_t pred_val = value;
2498 const VkImageSubresourceRange *range, bool value)
2503 uint64_t pred_val = value;
2576 /* Some default value we can set in the update. */
2600 /* Do not need to update the clear value for images that are fast cleared with the comp-to-single
2601 * mode because the hardware gets the value from the image directly.
2789 /* Disable constant encoding with the clear value of "1" with different DCC signedness
2790 * because the hardware will fill "1" instead of the clear value.
9227 VkClearDepthStencilValue value = {0};
9248 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);
9251 /* Initialize the TC-compat metada value to 0 because by
9253 * need have to conditionally update its value when performing
9296 const VkImageSubresourceRange *range, uint32_t value)
9303 return radv_clear_cmask(cmd_buffer, image, range, value);
9312 uint32_t value = fmask_clear_values[log2_samples];
9318 return radv_clear_fmask(cmd_buffer, image, range, value);
9323 const VkImageSubresourceRange *range, uint32_t value)
9332 flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
9383 uint32_t value;
9391 value = 0xccccccccu;
9393 value = 0xffffffffu;
9399 value = cmask_clear_values[log2_samples];
9402 flush_bits |= radv_init_cmask(cmd_buffer, image, range, value);
9410 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
9414 value = 0u;
9417 flush_bits |= radv_init_dcc(cmd_buffer, image, range, value);
9698 VkPipelineStageFlags2 stageMask, unsigned value)
9746 radeon_emit(cs, value);
9753 radeon_emit(cs, value);
9770 EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, value,
9848 /* By default, if the 32-bit value at offset in buffer memory is zero,
9851 * discarded if the value is non zero.
9866 * "If the 32-bit value at offset in buffer memory is zero,
9868 * are executed as normal. If the value of the predicate in
9872 * latch the value of the predicate upon beginning conditional
9877 * value which means we need a workaround in the driver.
9878 * Luckily, it's not required to support if the value changes
9882 * 1) allocate a 64-value in the upload BO and initialize it
9884 * 2) copy the 32-bit predicate value to the upload BO
10056 WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
10059 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */