Lines Matching defs:state
127 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
349 cmd_buffer->state.dirty |= dest_mask;
416 if (cmd_buffer->state.own_render_pass) {
418 radv_render_pass_to_handle(cmd_buffer->state.pass), NULL);
419 cmd_buffer->state.own_render_pass = false;
505 if (cmd_buffer->state.own_render_pass) {
507 radv_render_pass_to_handle(cmd_buffer->state.pass), NULL);
508 cmd_buffer->state.own_render_pass = false;
687 ++cmd_buffer->state.trace_id;
688 radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 1, &cmd_buffer->state.trace_id);
693 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
702 cmd_buffer->state.flush_bits & RADV_CMD_FLUSH_ALL_COMPUTE & ~RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
715 dst_stage_mask |= cmd_buffer->state.dma_is_busy ? VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV : 0;
868 if (cmd_buffer->state.graphics_pipeline && (flags & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) &&
869 radv_pipeline_has_stage(cmd_buffer->state.graphics_pipeline, MESA_SHADER_TASK)) {
1033 radv_convert_user_sample_locs(struct radv_sample_locations_state *state, uint32_t x, uint32_t y,
1036 uint32_t x_offset = x % state->grid_size.width;
1037 uint32_t y_offset = y % state->grid_size.height;
1038 uint32_t num_samples = (uint32_t)state->per_pixel;
1042 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
1045 user_locs = &state->locations[pixel_offset];
1126 struct radv_sample_locations_state *sample_location = &cmd_buffer->state.dynamic.sample_location;
1134 if (!cmd_buffer->state.dynamic.sample_location.count)
1202 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1226 struct radv_graphics_pipeline *old_pipeline = cmd_buffer->state.emitted_graphics_pipeline;
1236 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1243 const struct radv_graphics_pipeline *old_pipeline = cmd_buffer->state.emitted_graphics_pipeline;
1267 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1287 struct radv_cmd_state *state = &cmd_buffer->state;
1288 uint32_t mask = state->prefetch_L2_mask;
1301 si_cp_dma_prefetch(cmd_buffer, state->vb_va, pipeline->vb_desc_alloc_size);
1318 state->prefetch_L2_mask &= ~mask;
1327 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
1328 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1345 if (cmd_buffer->state.attachments) {
1346 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1356 VkFormat fmt = cmd_buffer->state.pass->attachments[idx].format;
1470 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1471 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1472 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1480 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1482 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1483 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1484 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1496 (!cmd_buffer->state.emitted_graphics_pipeline ||
1497 cmd_buffer->state.emitted_graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT] !=
1498 cmd_buffer->state.graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]) &&
1501 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) &&
1514 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
1516 if (cmd_buffer->state.emitted_graphics_pipeline == pipeline)
1526 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1527 cmd_buffer->state.emitted_graphics_pipeline->negative_one_to_one != pipeline->negative_one_to_one ||
1528 cmd_buffer->state.emitted_graphics_pipeline->depth_clamp_mode != pipeline->depth_clamp_mode)
1529 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1531 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1532 radv_rast_prim_is_points_or_lines(cmd_buffer->state.emitted_graphics_pipeline->rast_prim) != radv_rast_prim_is_points_or_lines(pipeline->rast_prim) ||
1533 cmd_buffer->state.emitted_graphics_pipeline->line_width != pipeline->line_width)
1534 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1536 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1537 cmd_buffer->state.emitted_graphics_pipeline->pa_su_sc_mode_cntl != pipeline->pa_su_sc_mode_cntl)
1538 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1542 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1543 cmd_buffer->state.emitted_graphics_pipeline->pa_cl_clip_cntl != pipeline->pa_cl_clip_cntl)
1544 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
1546 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1547 cmd_buffer->state.emitted_graphics_pipeline->cb_color_control != pipeline->cb_color_control)
1548 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
1550 if (!cmd_buffer->state.emitted_graphics_pipeline)
1551 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY |
1556 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1557 cmd_buffer->state.emitted_graphics_pipeline->db_depth_control != pipeline->db_depth_control)
1558 cmd_buffer->state.dirty |=
1563 if (!cmd_buffer->state.emitted_graphics_pipeline)
1564 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1566 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1567 cmd_buffer->state.emitted_graphics_pipeline->cb_target_mask != pipeline->cb_target_mask) {
1568 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE;
1575 !cmd_buffer->state.last_nggc_settings) {
1586 if (!cmd_buffer->state.emitted_graphics_pipeline ||
1587 cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs.cdw != pipeline->base.ctx_cs.cdw ||
1588 cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs_hash != pipeline->base.ctx_cs_hash ||
1589 memcmp(cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs.buf, pipeline->base.ctx_cs.buf,
1592 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1602 cmd_buffer->state.emitted_graphics_pipeline = pipeline;
1604 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1610 const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
1611 const struct radv_viewport_state *viewport = &cmd_buffer->state.dynamic.viewport;
1657 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
1658 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1669 rast_prim = si_conv_prim_to_gs_out(cmd_buffer->state.dynamic.primitive_topology);
1672 si_write_scissors(cs, 0, count, cmd_buffer->state.dynamic.scissor.scissors,
1673 cmd_buffer->state.dynamic.viewport.viewports, rast_prim,
1674 cmd_buffer->state.dynamic.line_width);
1682 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1688 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1692 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1693 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1694 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1704 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1713 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1722 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1738 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1748 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1762 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1777 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.graphics_pipeline->pa_su_sc_mode_cntl;
1778 const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1807 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1809 assert(!cmd_buffer->state.mesh_shading);
1822 unsigned db_depth_control = cmd_buffer->state.graphics_pipeline->db_depth_control;
1823 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1849 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1864 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
1865 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1866 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1910 if (cmd_buffer->state.mesh_shading) {
1929 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1946 unsigned pa_cl_clip_cntl = cmd_buffer->state.graphics_pipeline->pa_cl_clip_cntl;
1947 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1958 unsigned cb_color_control = cmd_buffer->state.graphics_pipeline->cb_color_control;
1959 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1970 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
1971 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
2171 !cmd_buffer->state.subpass->vrs_attachment) {
2257 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2262 if (!cmd_buffer->state.attachments || !subpass)
2269 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2290 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds, iview,
2294 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2312 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
2335 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
2360 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
2494 * Update the DCC predicate to reflect the compression state.
2529 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2533 if (!cmd_buffer->state.attachments || !subpass)
2540 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2547 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2566 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2637 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2643 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2651 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2665 struct vk_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2666 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2681 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2685 radv_dcc_enabled(iview->image, cmd_buffer->state.cb_mip[i])) &&
2686 cmd_buffer->state.cb_mip[i] != iview->vk.base_mip_level)
2689 cmd_buffer->state.cb_mip[i] = iview->vk.base_mip_level;
2693 cmd_buffer->state.flush_bits |=
2711 if (cmd_buffer->state.cb_mip[i]) {
2718 cmd_buffer->state.flush_bits |=
2722 memset(cmd_buffer->state.cb_mip, 0, sizeof(cmd_buffer->state.cb_mip));
2733 /* The global VRS state is initialized on-demand to avoid wasting VRAM. */
2748 struct vk_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2749 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2762 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2782 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout,
2795 for (; i < cmd_buffer->state.last_subpass_color_count; i++) {
2798 cmd_buffer->state.last_subpass_color_count = subpass->color_count;
2804 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2806 cmd_buffer->state.attachments[idx].iview->image->bindings[0].bo);
2808 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout,
2893 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2900 struct radv_cmd_state *state = &cmd_buffer->state;
2904 if (state->index_type < 0)
2912 if (state->max_index_count ||
2915 radeon_emit(cs, state->index_va);
2916 radeon_emit(cs, state->index_va >> 32);
2919 radeon_emit(cs, state->max_index_count);
2922 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2928 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2929 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
2947 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2979 cmd_buffer->state.context_roll_without_scissor_emitted = true;
3061 const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
3062 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
3068 uint32_t instance_rate_inputs = state->instance_rate_inputs & attribute_mask;
3069 uint32_t zero_divisors = state->zero_divisors & attribute_mask;
3070 *nontrivial_divisors = state->nontrivial_divisors & attribute_mask;
3071 uint32_t misaligned_mask = cmd_buffer->state.vbo_misaligned_mask;
3072 if (cmd_buffer->state.vbo_misaligned_mask_invalid) {
3076 u_foreach_bit (index, cmd_buffer->state.vbo_misaligned_mask_invalid & attribute_mask) {
3077 uint8_t binding = state->bindings[index];
3078 if (!(cmd_buffer->state.vbo_bound_mask & BITFIELD_BIT(binding)))
3080 uint8_t req = state->format_align_req_minus_1[index];
3082 VkDeviceSize offset = vb->offset + state->offsets[index];
3086 cmd_buffer->state.vbo_misaligned_mask = misaligned_mask;
3087 cmd_buffer->state.vbo_misaligned_mask_invalid &= ~attribute_mask;
3094 !misaligned_mask && !state->alpha_adjust_lo && !state->alpha_adjust_hi) {
3112 key.state = state;
3147 u_foreach_bit(index, misaligned_mask) formats[num_formats++] = state->formats[index];
3152 if (state->post_shuffle & attribute_mask) {
3154 key_words[key_size++] = state->post_shuffle & attribute_mask;
3157 if (state->alpha_adjust_lo & attribute_mask) {
3159 key_words[key_size++] = state->alpha_adjust_lo & attribute_mask;
3161 if (state->alpha_adjust_hi & attribute_mask) {
3163 key_words[key_size++] = state->alpha_adjust_hi & attribute_mask;
3171 if (cmd_buffer->state.emitted_vs_prolog &&
3172 cmd_buffer->state.emitted_vs_prolog_key_hash == hash &&
3173 radv_cmp_vs_prolog(key_words, cmd_buffer->state.emitted_vs_prolog_key))
3174 return cmd_buffer->state.emitted_vs_prolog;
3212 if (cmd_buffer->state.emitted_vs_prolog == prolog && !pipeline_is_dirty)
3216 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
3219 assert(cmd_buffer->state.emitted_graphics_pipeline == cmd_buffer->state.graphics_pipeline);
3261 if (!nontrivial_divisors && !pipeline_is_dirty && cmd_buffer->state.emitted_vs_prolog &&
3262 !cmd_buffer->state.emitted_vs_prolog->nontrivial_divisors)
3265 const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
3280 uint32_t div = state->divisors[index];
3299 uint32_t base_reg = cmd_buffer->state.graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX];
3309 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
3312 assert(!cmd_buffer->state.mesh_shading);
3327 cmd_buffer->state.emitted_vs_prolog = prolog;
3337 cmd_buffer->state.dirty & cmd_buffer->state.emitted_graphics_pipeline->needed_dynamic_state;
3406 cmd_buffer->state.dirty &= ~states;
3517 if (!cmd_buffer->state.graphics_pipeline->base.shaders[stage])
3709 vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
3717 vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]
3853 if ((pipeline_is_dirty || (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
3854 cmd_buffer->state.graphics_pipeline->vb_desc_usage_mask) {
3856 assert(!cmd_buffer->state.mesh_shading);
3858 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
3863 /* allocate some descriptor state for vertex buffers */
3876 cmd_buffer->state.vb_va = va;
3877 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
3882 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
3888 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
3920 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
3922 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
3927 /* Allocate some descriptor state for streamout buffers. */
3983 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
3989 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
4005 if (cmd_buffer->state.active_pipeline_gds_queries ||
4006 (cmd_buffer->state.inherited_pipeline_statistics &
4019 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
4028 cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;
4051 if (cmd_buffer->state.last_vrs_rates != vrs_rates ||
4052 cmd_buffer->state.last_vrs_rates_sgpr_idx != loc->sgpr_idx) {
4056 cmd_buffer->state.last_vrs_rates = vrs_rates;
4057 cmd_buffer->state.last_vrs_rates_sgpr_idx = loc->sgpr_idx;
4063 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
4119 uint32_t index_type = G_028A7C_INDEX_TYPE(cmd_buffer->state.index_type);
4138 struct radv_cmd_state *state = &cmd_buffer->state;
4139 unsigned topology = state->dynamic.primitive_topology;
4140 bool prim_restart_enable = state->dynamic.primitive_restart_enable;
4148 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
4157 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
4165 struct radv_cmd_state *state = &cmd_buffer->state;
4167 uint32_t topology = state->dynamic.primitive_topology;
4170 /* Draw state. */
4177 if (state->dynamic.primitive_restart_enable) {
4180 if (primitive_reset_index != state->last_primitive_reset_index) {
4182 state->last_primitive_reset_index = primitive_reset_index;
4222 if (info->gfx_level == GFX10_3 && state->active_pipeline_queries > 0 &&
4229 if ((draw_info->indexed && state->index_type != state->last_index_type) ||
4231 (state->last_index_type == -1 ||
4232 disable_instance_packing != G_028A7C_DISABLE_INSTANCE_PACKING(state->last_index_type)))) {
4233 uint32_t index_type = state->index_type | S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing);
4243 state->last_index_type = index_type;
4270 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
4278 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4288 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
4314 * bring the caches to a "state of rest", which none of the caches below that
4319 * For GFX9+ we can define the state at rest to be L2 instead of VRAM for all
4430 can_skip_buffer_l2_flushes(cmd_buffer->device) && !cmd_buffer->state.rb_noncoherent_dirty;
4528 struct radv_render_pass *pass = cmd_buffer->state.pass;
4531 struct radv_image_view *iview = cmd_buffer->state.attachments[i].iview;
4533 cmd_buffer->state.flush_bits |=
4540 struct radv_image_view *iview = cmd_buffer->state.attachments[i].iview;
4542 cmd_buffer->state.flush_bits |=
4552 struct radv_cmd_state *state = &cmd_buffer->state;
4553 uint32_t subpass_id = state->subpass - state->pass->subpasses;
4558 assert(subpass_id < state->pass->subpass_count);
4566 struct radv_cmd_state *state = &cmd_buffer->state;
4568 struct radv_image_view *view = state->attachments[att_idx].iview;
4573 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
4577 if (state->attachments[att_idx].sample_location.count > 0)
4578 return &state->attachments[att_idx].sample_location;
4581 if (state->subpass_sample_locs) {
4592 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
4593 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
4594 return &state->subpass_sample_locs[i].sample_location;
4607 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
4614 range.layerCount = cmd_buffer->state.framebuffer->layers;
4616 if (cmd_buffer->state.subpass->view_mask) {
4624 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
4634 if ((cmd_buffer->state.attachments[idx].current_layout !=
4635 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
4648 cmd_buffer->state.attachments[idx].current_layout,
4649 cmd_buffer->state.attachments[idx].current_in_render_loop,
4655 cmd_buffer, view->image, cmd_buffer->state.attachments[idx].current_stencil_layout,
4656 cmd_buffer->state.attachments[idx].current_in_render_loop, att.stencil_layout,
4660 cmd_buffer->state.attachments[idx].current_layout,
4661 cmd_buffer->state.attachments[idx].current_in_render_loop,
4665 cmd_buffer->state.attachments[idx].current_layout = att.layout;
4666 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
4667 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
4673 cmd_buffer->state.subpass = subpass;
4675 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
4685 struct radv_cmd_state *state = &cmd_buffer->state;
4688 state->subpass_sample_locs = NULL;
4696 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
4713 state->attachments[att_idx].sample_location.per_pixel =
4715 state->attachments[att_idx].sample_location.grid_size =
4717 state->attachments[att_idx].sample_location.count = sample_locs_info->sampleLocationsCount;
4718 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
4722 state->subpass_sample_locs =
4724 sample_locs->postSubpassSampleLocationsCount * sizeof(state->subpass_sample_locs[0]),
4726 if (state->subpass_sample_locs == NULL) {
4731 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
4739 state->subpass_sample_locs[i].subpass_idx = subpass_sample_locs_info->subpassIndex;
4740 state->subpass_sample_locs[i].sample_location.per_pixel =
4742 state->subpass_sample_locs[i].sample_location.grid_size =
4744 state->subpass_sample_locs[i].sample_location.count = sample_locs_info->sampleLocationsCount;
4745 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
4756 struct radv_cmd_state *state = &cmd_buffer->state;
4764 state->attachments = NULL;
4768 state->attachments =
4769 vk_alloc(&cmd_buffer->pool->vk.alloc, pass->attachment_count * sizeof(state->attachments[0]),
4771 if (state->attachments == NULL) {
4801 state->attachments[i].pending_clear_aspects = clear_aspects;
4802 state->attachments[i].cleared_views = 0;
4805 state->attachments[i].clear_value = info->pClearValues[i];
4808 state->attachments[i].current_layout = att->initial_layout;
4809 state->attachments[i].current_in_render_loop = false;
4810 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
4811 state->attachments[i].sample_location.count = 0;
4817 iview = radv_image_view_from_handle(state->framebuffer->attachments[i]);
4820 state->attachments[i].iview = iview;
4822 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
4824 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
5000 cmd_buffer->state.pass = radv_render_pass_from_handle(rp);
5001 cmd_buffer->state.own_render_pass = true;
5019 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
5020 cmd_buffer->state.last_primitive_reset_en = -1;
5021 cmd_buffer->state.last_index_type = -1;
5022 cmd_buffer->state.last_num_instances = -1;
5023 cmd_buffer->state.last_vertex_offset = -1;
5024 cmd_buffer->state.last_first_instance = -1;
5025 cmd_buffer->state.last_drawid = -1;
5026 cmd_buffer->state.last_subpass_color_count = MAX_RTS;
5027 cmd_buffer->state.predication_type = -1;
5028 cmd_buffer->state.last_sx_ps_downconvert = -1;
5029 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
5030 cmd_buffer->state.last_sx_blend_opt_control = -1;
5031 cmd_buffer->state.last_nggc_settings = -1;
5032 cmd_buffer->state.last_nggc_settings_sgpr_idx = -1;
5033 cmd_buffer->state.mesh_shading = false;
5034 cmd_buffer->state.last_vrs_rates = -1;
5035 cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;
5044 cmd_buffer->state.framebuffer =
5048 cmd_buffer->state.pass =
5050 assert(pBeginInfo->pInheritanceInfo->subpass < cmd_buffer->state.pass->subpass_count);
5051 subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
5058 subpass = &cmd_buffer->state.pass->subpasses[0];
5062 if (cmd_buffer->state.framebuffer) {
5063 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
5068 cmd_buffer->state.inherited_pipeline_statistics =
5071 if (cmd_buffer->state.pass) {
5072 cmd_buffer->state.subpass = subpass;
5073 if (cmd_buffer->state.framebuffer)
5074 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
5096 const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
5119 misaligned_mask_invalid |= state->bindings_match_attrib ? BITFIELD_BIT(idx) : 0xffffffff;
5130 cmd_buffer->state.vbo_bound_mask |= bit;
5132 cmd_buffer->state.vbo_bound_mask &= ~bit;
5137 cmd_buffer->state.vbo_misaligned_mask_invalid = misaligned_mask_invalid;
5138 cmd_buffer->state.vbo_misaligned_mask &= ~misaligned_mask_invalid;
5141 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER |
5183 cmd_buffer->state.index_buffer = index_buffer;
5184 cmd_buffer->state.index_offset = offset;
5185 cmd_buffer->state.index_type = vk_to_index_type(indexType);
5186 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
5187 cmd_buffer->state.index_va += index_buffer->offset + offset;
5190 cmd_buffer->state.max_index_count =
5192 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5434 cmd_buffer->state.flush_bits |=
5440 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
5445 if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))
5446 cmd_buffer->state.flush_bits |= radv_src_access_flush(
5457 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
5476 vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.attachments);
5477 vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.subpass_sample_locs);
5492 if (pipeline == cmd_buffer->state.emitted_compute_pipeline)
5497 cmd_buffer->state.emitted_compute_pipeline = pipeline;
5533 if (cmd_buffer->state.compute_pipeline == compute_pipeline)
5537 cmd_buffer->state.compute_pipeline = compute_pipeline;
5546 if (cmd_buffer->state.rt_pipeline == compute_pipeline)
5550 cmd_buffer->state.rt_pipeline = compute_pipeline;
5553 radv_set_rt_stack_size(cmd_buffer, cmd_buffer->state.rt_stack_size);
5560 if (cmd_buffer->state.graphics_pipeline == graphics_pipeline)
5565 !pipeline || !cmd_buffer->state.graphics_pipeline ||
5566 cmd_buffer->state.graphics_pipeline->vtx_emit_num != graphics_pipeline->vtx_emit_num ||
5567 cmd_buffer->state.graphics_pipeline->vtx_base_sgpr != graphics_pipeline->vtx_base_sgpr;
5568 cmd_buffer->state.graphics_pipeline = graphics_pipeline;
5573 if (mesh_shading != cmd_buffer->state.mesh_shading) {
5574 /* Re-emit VRS state because the combiner is different (vertex vs primitive).
5577 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE |
5581 cmd_buffer->state.mesh_shading = mesh_shading;
5582 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE | RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT;
5587 cmd_buffer->state.last_first_instance = -1;
5588 cmd_buffer->state.last_vertex_offset = -1;
5589 cmd_buffer->state.last_drawid = -1;
5593 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
5596 cmd_buffer->state.emitted_graphics_pipeline &&
5597 cmd_buffer->state.emitted_graphics_pipeline->is_ngg &&
5598 !cmd_buffer->state.graphics_pipeline->is_ngg) {
5604 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
5642 struct radv_cmd_state *state = &cmd_buffer->state;
5648 if (state->dynamic.viewport.count < total_count)
5649 state->dynamic.viewport.count = total_count;
5651 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
5655 state->dynamic.viewport.xform[i + firstViewport].scale,
5656 state->dynamic.viewport.xform[i + firstViewport].translate);
5659 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
5667 struct radv_cmd_state *state = &cmd_buffer->state;
5673 if (state->dynamic.scissor.count < total_count)
5674 state->dynamic.scissor.count = total_count;
5676 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
5679 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
5687 if (cmd_buffer->state.dynamic.line_width != lineWidth)
5688 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
5690 cmd_buffer->state.dynamic.line_width = lineWidth;
5691 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
5699 struct radv_cmd_state *state = &cmd_buffer->state;
5701 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
5702 state->dynamic.depth_bias.clamp = depthBiasClamp;
5703 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
5705 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
5712 struct radv_cmd_state *state = &cmd_buffer->state;
5714 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
5716 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
5723 struct radv_cmd_state *state = &cmd_buffer->state;
5725 state->dynamic.depth_bounds.min = minDepthBounds;
5726 state->dynamic.depth_bounds.max = maxDepthBounds;
5728 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
5736 struct radv_cmd_state *state = &cmd_buffer->state;
5739 state->dynamic.stencil_compare_mask.front = compareMask;
5741 state->dynamic.stencil_compare_mask.back = compareMask;
5743 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
5751 struct radv_cmd_state *state = &cmd_buffer->state;
5754 state->dynamic.stencil_write_mask.front = writeMask;
5756 state->dynamic.stencil_write_mask.back = writeMask;
5758 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
5768 cmd_buffer->state.dynamic.stencil_reference.front = reference;
5770 cmd_buffer->state.dynamic.stencil_reference.back = reference;
5772 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
5780 struct radv_cmd_state *state = &cmd_buffer->state;
5786 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
5789 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
5797 struct radv_cmd_state *state = &cmd_buffer->state;
5801 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
5802 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
5803 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
5804 typed_memcpy(&state->dynamic.sample_location.locations[0],
5807 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
5815 struct radv_cmd_state *state = &cmd_buffer->state;
5817 state->dynamic.line_stipple.factor = lineStippleFactor;
5818 state->dynamic.line_stipple.pattern = lineStipplePattern;
5820 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
5827 struct radv_cmd_state *state = &cmd_buffer->state;
5829 state->dynamic.cull_mode = cullMode;
5831 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
5838 struct radv_cmd_state *state = &cmd_buffer->state;
5840 state->dynamic.front_face = frontFace;
5842 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
5849 struct radv_cmd_state *state = &cmd_buffer->state;
5852 if ((state->dynamic.primitive_topology == V_008958_DI_PT_LINESTRIP) !=
5854 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
5856 if (radv_prim_is_points_or_lines(state->dynamic.primitive_topology) !=
5858 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
5860 state->dynamic.primitive_topology = primitive_topology;
5862 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
5884 struct radv_cmd_state *state = &cmd_buffer->state;
5886 state->dynamic.depth_test_enable = depthTestEnable;
5888 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
5895 struct radv_cmd_state *state = &cmd_buffer->state;
5897 state->dynamic.depth_write_enable = depthWriteEnable;
5899 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
5906 struct radv_cmd_state *state = &cmd_buffer->state;
5908 state->dynamic.depth_compare_op = depthCompareOp;
5910 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
5917 struct radv_cmd_state *state = &cmd_buffer->state;
5919 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
5921 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
5928 struct radv_cmd_state *state = &cmd_buffer->state;
5930 state->dynamic.stencil_test_enable = stencilTestEnable;
5932 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
5941 struct radv_cmd_state *state = &cmd_buffer->state;
5944 state->dynamic.stencil_op.front.fail_op = failOp;
5945 state->dynamic.stencil_op.front.pass_op = passOp;
5946 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
5947 state->dynamic.stencil_op.front.compare_op = compareOp;
5951 state->dynamic.stencil_op.back.fail_op = failOp;
5952 state->dynamic.stencil_op.back.pass_op = passOp;
5953 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
5954 state->dynamic.stencil_op.back.compare_op = compareOp;
5957 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
5965 struct radv_cmd_state *state = &cmd_buffer->state;
5967 state->dynamic.fragment_shading_rate.size = *pFragmentSize;
5969 state->dynamic.fragment_shading_rate.combiner_ops[i] = combinerOps[i];
5971 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
5978 struct radv_cmd_state *state = &cmd_buffer->state;
5980 state->dynamic.depth_bias_enable = depthBiasEnable;
5982 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE;
5989 struct radv_cmd_state *state = &cmd_buffer->state;
5991 state->dynamic.primitive_restart_enable = primitiveRestartEnable;
5993 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE;
6000 struct radv_cmd_state *state = &cmd_buffer->state;
6002 state->dynamic.rasterizer_discard_enable = rasterizerDiscardEnable;
6004 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
6017 struct radv_cmd_state *state = &cmd_buffer->state;
6020 state->dynamic.logic_op = logic_op;
6022 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
6030 struct radv_cmd_state *state = &cmd_buffer->state;
6039 state->dynamic.color_write_enable = color_write_enable;
6041 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE;
6051 struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
6057 cmd_buffer->state.vbo_misaligned_mask = 0;
6058 cmd_buffer->state.vbo_misaligned_mask_invalid = 0;
6060 memset(state, 0, sizeof(*state));
6061 state->bindings_match_attrib = true;
6069 state->attribute_mask |= 1u << loc;
6070 state->bindings[loc] = attrib->binding;
6072 state->bindings_match_attrib = false;
6074 state->instance_rate_inputs |= 1u << loc;
6075 state->divisors[loc] = binding->divisor;
6077 state->zero_divisors |= 1u << loc;
6079 state->nontrivial_divisors |= 1u << loc;
6083 state->offsets[loc] = attrib->offset;
6115 state->formats[loc] = found->hw_fmt;
6116 state->format_align_req_minus_1[loc] = found->fmt_align_req_minus_1;
6117 state->format_sizes[loc] = found->fmt_size;
6118 state->alpha_adjust_lo |= found->alpha_adjust_lo << loc;
6119 state->alpha_adjust_hi |= found->alpha_adjust_hi << loc;
6121 state->post_shuffle |= 1u << loc;
6124 cmd_buffer->state.vbo_bound_mask & BITFIELD_BIT(attrib->binding)) {
6126 cmd_buffer->state.vbo_misaligned_mask |= BITFIELD_BIT(loc);
6127 } else if ((cmd_buffer->vertex_bindings[attrib->binding].offset + state->offsets[loc]) &
6129 cmd_buffer->state.vbo_misaligned_mask |= BITFIELD_BIT(loc);
6134 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER |
6159 secondary->state.uses_draw_indirect_multi) {
6196 if (!secondary->state.framebuffer && primary->state.pass && (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
6197 /* Emit the framebuffer state from primary if secondary
6243 if (secondary->state.emitted_graphics_pipeline) {
6244 primary->state.emitted_graphics_pipeline = secondary->state.emitted_graphics_pipeline;
6250 if (secondary->state.emitted_compute_pipeline) {
6251 primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
6255 if (secondary->state.last_primitive_reset_en != -1) {
6256 primary->state.last_primitive_reset_en = secondary->state.last_primitive_reset_en;
6259 if (secondary->state.last_primitive_reset_index) {
6260 primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index;
6263 if (secondary->state.last_ia_multi_vgt_param) {
6264 primary->state.last_ia_multi_vgt_param = secondary->state.last_ia_multi_vgt_param;
6267 primary->state.last_first_instance = secondary->state.last_first_instance;
6268 primary->state.last_num_instances = secondary->state.last_num_instances;
6269 primary->state.last_drawid = secondary->state.last_drawid;
6270 primary->state.last_subpass_color_count = secondary->state.last_subpass_color_count;
6271 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
6272 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
6273 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
6274 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
6276 if (secondary->state.last_index_type != -1) {
6277 primary->state.last_index_type = secondary->state.last_index_type;
6280 primary->state.last_nggc_settings = secondary->state.last_nggc_settings;
6281 primary->state.last_nggc_settings_sgpr_idx = secondary->state.last_nggc_settings_sgpr_idx;
6282 primary->state.last_nggc_skip = secondary->state.last_nggc_skip;
6284 primary->state.last_vrs_rates = secondary->state.last_vrs_rates;
6285 primary->state.last_vrs_rates_sgpr_idx = secondary->state.last_vrs_rates_sgpr_idx;
6291 primary->state.dirty |=
6377 struct radv_cmd_state *state = &cmd_buffer->state;
6378 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
6403 struct radv_image_view *vrs_iview = cmd_buffer->state.attachments[idx].iview;
6410 struct radv_image_view *ds_iview = cmd_buffer->state.attachments[ds_idx].iview;
6435 struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
6459 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
6462 if (!cmd_buffer->state.attachments) {
6463 cmd_buffer->state.rb_noncoherent_dirty = true;
6471 if (!cmd_buffer->state.attachments[a].iview->image->l2_coherent) {
6472 cmd_buffer->state.rb_noncoherent_dirty = true;
6477 !cmd_buffer->state.attachments[subpass->depth_stencil_attachment->attachment]
6479 cmd_buffer->state.rb_noncoherent_dirty = true;
6493 struct radv_cmd_state *state = &cmd_buffer->state;
6494 const struct radv_subpass *subpass = state->subpass;
6506 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
6509 VkImageLayout layout = state->pass->attachments[a].final_layout;
6510 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
6529 cmd_buffer->state.framebuffer = framebuffer;
6530 cmd_buffer->state.pass = pass;
6531 cmd_buffer->state.render_area = pRenderPassBeginInfo->renderArea;
6571 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
6599 radv_cs_emit_compute_predication(struct radv_cmd_state *state, struct radeon_cmdbuf *cs,
6602 if (!state->predicating)
6605 uint64_t va = state->predication_va;
6607 if (!state->predication_type) {
6652 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
6668 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
6687 bool draw_id_enable = cmd_buffer->state.graphics_pipeline->uses_drawid;
6688 uint32_t base_reg = cmd_buffer->state.graphics_pipeline->vtx_base_sgpr;
6690 bool predicating = cmd_buffer->state.predicating;
6691 bool mesh = cmd_buffer->state.mesh_shading;
6694 /* just reset draw state for vertex data */
6695 cmd_buffer->state.last_first_instance = -1;
6696 cmd_buffer->state.last_num_instances = -1;
6697 cmd_buffer->state.last_drawid = -1;
6698 cmd_buffer->state.last_vertex_offset = -1;
6701 if (cmd_buffer->state.graphics_pipeline->uses_baseinstance)
6727 cmd_buffer->state.uses_draw_indirect_multi = true;
6736 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6739 const bool predicating = cmd_buffer->state.predicating;
6766 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6815 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6817 bool predicating = cmd_buffer->state.predicating;
6824 uint32_t base_reg = cmd_buffer->state.graphics_pipeline->vtx_base_sgpr;
6838 struct radv_cmd_state *state = &cmd_buffer->state;
6840 const bool uses_baseinstance = state->graphics_pipeline->uses_baseinstance;
6841 const bool uses_drawid = state->graphics_pipeline->uses_drawid;
6843 radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, state->graphics_pipeline->vtx_emit_num);
6846 state->last_vertex_offset = vertex_offset;
6849 state->last_drawid = 0;
6853 state->last_first_instance = info->first_instance;
6861 const struct radv_cmd_state *state = &cmd_buffer->state;
6862 const bool uses_baseinstance = state->graphics_pipeline->uses_baseinstance;
6863 const bool uses_drawid = state->graphics_pipeline->uses_drawid;
6868 if (vertex_offset != state->last_vertex_offset) {
6870 } else if (uses_drawid && 0 != state->last_drawid) {
6872 } else if (uses_baseinstance && info->first_instance != state->last_first_instance) {
6880 struct radv_cmd_state *state = &cmd_buffer->state;
6882 radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, 1 + !!drawid);
6884 state->last_vertex_offset = vertex_offset;
6895 struct radv_cmd_state *state = &cmd_buffer->state;
6897 const bool uses_drawid = state->graphics_pipeline->uses_drawid;
6899 radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, state->graphics_pipeline->vtx_emit_num);
6907 state->last_drawid = 0;
6914 struct radv_cmd_state *state = &cmd_buffer->state;
6916 struct radv_graphics_pipeline *pipeline = state->graphics_pipeline;
6932 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6953 struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
6990 struct radv_cmd_state *state = &cmd_buffer->state;
6992 const int index_size = radv_get_vgt_index_size(state->index_type);
6994 const bool uses_drawid = state->graphics_pipeline->uses_drawid;
7002 const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
7010 radeon_set_sh_reg(cs, state->graphics_pipeline->vtx_base_sgpr + sizeof(uint32_t), i);
7012 const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
7014 if (!state->subpass->view_mask) {
7017 u_foreach_bit(view, state->subpass->view_mask) {
7026 const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
7034 if (state->last_vertex_offset != draw->vertexOffset)
7037 radeon_set_sh_reg(cs, state->graphics_pipeline->vtx_base_sgpr + sizeof(uint32_t), i);
7041 const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
7043 if (!state->subpass->view_mask) {
7046 u_foreach_bit(view, state->subpass->view_mask) {
7055 state->last_drawid = drawCount - 1;
7073 const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
7080 const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
7082 if (!state->subpass->view_mask) {
7085 u_foreach_bit(view, state->subpass->view_mask) {
7094 const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
7105 const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
7107 if (!state->subpass->view_mask) {
7110 u_foreach_bit(view, state->subpass->view_mask) {
7119 state->last_drawid = drawCount - 1;
7130 const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
7131 const bool uses_drawid = cmd_buffer->state.graphics_pipeline->uses_drawid;
7151 struct radv_cmd_state *state = &cmd_buffer->state;
7152 state->last_vertex_offset = last_start;
7154 state->last_drawid = drawCount - 1;
7163 const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
7183 const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
7197 radv_cs_emit_compute_predication(&cmd_buffer->state, cmd_buffer->ace_internal.cs,
7218 const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
7270 radv_cs_emit_compute_predication(&cmd_buffer->state, cmd_buffer->ace_internal.cs,
7321 const struct radv_cmd_state *state = &cmd_buffer->state;
7342 if (!state->subpass->view_mask) {
7346 u_foreach_bit(i, state->subpass->view_mask)
7376 struct radv_cmd_state *state = &cmd_buffer->state;
7381 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
7385 cmd_buffer->state.graphics_pipeline->needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
7394 if (cmd_buffer->state.dirty & used_states)
7399 if (info->indexed && state->dynamic.primitive_restart_enable &&
7400 primitive_reset_index != state->last_primitive_reset_index)
7422 const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
7423 const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
7427 G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.graphics_pipeline->pa_cl_clip_cntl))
7430 uint32_t pa_su_sc_mode_cntl = cmd_buffer->state.graphics_pipeline->pa_su_sc_mode_cntl;
7475 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
7479 if (!nggc_supported && !cmd_buffer->state.last_nggc_settings) {
7483 cmd_buffer->state.last_nggc_settings_sgpr_idx = -1;
7492 cmd_buffer->state.dirty &
7504 if (!dirty && skip == cmd_buffer->state.last_nggc_skip)
7507 /* Remember small draw state. */
7508 cmd_buffer->state.last_nggc_skip = skip;
7519 memcpy(vp_scale, cmd_buffer->state.dynamic.viewport.xform[0].scale, 2 * sizeof(float));
7520 memcpy(vp_translate, cmd_buffer->state.dynamic.viewport.xform[0].translate, 2 * sizeof(float));
7529 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_VIEWPORT ||
7530 cmd_buffer->state.last_nggc_settings_sgpr_idx != nggc_sgpr_idx ||
7531 !cmd_buffer->state.last_nggc_settings);
7554 (cmd_buffer->state.last_nggc_settings != nggc_settings ||
7555 cmd_buffer->state.last_nggc_settings_sgpr_idx != nggc_sgpr_idx);
7568 if (!!cmd_buffer->state.last_nggc_settings != !!nggc_settings) {
7580 if (!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) ||
7581 cmd_buffer->state.emitted_graphics_pipeline == pipeline) {
7586 cmd_buffer->state.last_nggc_settings = nggc_settings;
7587 cmd_buffer->state.last_nggc_settings_sgpr_idx = nggc_sgpr_idx;
7596 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
7597 cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline)
7601 cmd_buffer->state.graphics_pipeline->is_ngg)
7604 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
7607 /* This should be before the cmd_buffer->state.dirty is cleared
7609 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
7612 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
7616 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
7620 * so the state must be re-emitted before the next indexed
7624 cmd_buffer->state.last_index_type = -1;
7625 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
7630 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
7632 cmd_buffer->state.dirty & cmd_buffer->state.emitted_graphics_pipeline->needed_dynamic_state;
7642 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
7659 const bool pipeline_is_dirty = (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
7660 cmd_buffer->state.graphics_pipeline != cmd_buffer->state.emitted_graphics_pipeline;
7679 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
7685 if (cmd_buffer->state.flush_bits &
7706 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
7710 radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.graphics_pipeline, true);
7720 struct radv_cmd_state *state = &cmd_buffer->state;
7722 assert(state->graphics_pipeline->vtx_base_sgpr);
7723 if (state->last_num_instances != info->instance_count) {
7726 state->last_num_instances = info->instance_count;
7741 cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE &&
7742 cmd_buffer->state.graphics_pipeline != cmd_buffer->state.emitted_graphics_pipeline;
7747 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
7779 /* Restore dirty state of descriptors
7805 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
7806 radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.graphics_pipeline, false);
7815 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
7872 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
7880 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
7955 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
8166 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
8197 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
8259 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
8336 const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
8338 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
8358 cmd_buffer->state.last_index_type = -1;
8359 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
8363 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
8366 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
8370 cmd_buffer->state.last_index_type = -1;
8371 cmd_buffer->state.last_num_instances = -1;
8372 cmd_buffer->state.last_vertex_offset = -1;
8373 cmd_buffer->state.last_first_instance = -1;
8374 cmd_buffer->state.last_drawid = -1;
8410 bool predicating = cmd_buffer->state.predicating;
8454 radv_cs_emit_compute_predication(&cmd_buffer->state, cs, cmd_buffer->mec_inv_pred_va,
8539 radv_cs_emit_compute_predication(&cmd_buffer->state, cs, cmd_buffer->mec_inv_pred_va,
8573 bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;
8576 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
8579 if (cmd_buffer->state.flush_bits &
8635 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
8643 radv_dispatch(cmd_buffer, info, cmd_buffer->state.compute_pipeline,
8717 struct radv_compute_pipeline *pipeline = cmd_buffer->state.rt_pipeline;
8845 if (cmd_buffer->state.rt_pipeline) {
8846 scratch_bytes_per_wave = cmd_buffer->state.rt_pipeline->base.scratch_bytes_per_wave;
8847 wave_size = cmd_buffer->state.rt_pipeline->base.shaders[MESA_SHADER_COMPUTE]->info.wave_size;
8863 cmd_buffer->state.rt_stack_size = size;
8873 radv_emit_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
8877 vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.attachments);
8878 vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.subpass_sample_locs);
8880 cmd_buffer->state.pass = NULL;
8881 cmd_buffer->state.subpass = NULL;
8882 cmd_buffer->state.attachments = NULL;
8883 cmd_buffer->state.framebuffer = NULL;
8884 cmd_buffer->state.subpass_sample_locs = NULL;
9203 struct radv_render_pass *pass = cmd_buffer->state.pass;
9204 struct vk_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
9225 struct radv_cmd_state *state = &cmd_buffer->state;
9235 state->flush_bits |=
9243 state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image);
9246 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
9284 cmd_buffer->state.flush_bits |=
9289 cmd_buffer->state.flush_bits |=
9379 cmd_buffer->state.flush_bits |=
9427 cmd_buffer->state.flush_bits |= flush_bits;
9478 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu);
9514 * a state where DCC is compressed and the main
9602 if (cmd_buffer->state.subpass)
9649 cmd_buffer->state.flush_bits |= src_flush_bits;
9682 cmd_buffer->state.flush_bits |= dst_flush_bits;
9915 cmd_buffer->state.predicating = true;
9916 cmd_buffer->state.predication_type = draw_visible;
9917 cmd_buffer->state.predication_op = pred_op;
9918 cmd_buffer->state.predication_va = va;
9933 cmd_buffer->state.predicating = false;
9934 cmd_buffer->state.predication_type = -1;
9935 cmd_buffer->state.predication_op = 0;
9936 cmd_buffer->state.predication_va = 0;
9968 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
9970 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
9976 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
9979 return (so->streamout_enabled || cmd_buffer->state.prims_gen_query_enabled) &&
9980 !cmd_buffer->state.suspend_streamout;
9986 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
9987 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
10003 cmd_buffer->state.context_roll_without_scissor_emitted = true;
10009 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
10071 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
10072 struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
10093 cmd_buffer->state.context_roll_without_scissor_emitted = true;
10136 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
10148 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
10208 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
10250 cmd_buffer->state.context_roll_without_scissor_emitted = true;
10261 struct radv_streamout_state *so = &cmd_buffer->state.streamout;