Lines Matching defs:range
61 uint32_t dst_family_index, const VkImageSubresourceRange *range,
2096 VkImageSubresourceRange range = {
2104 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
2302 const VkImageSubresourceRange *range,
2306 uint32_t level_count = radv_get_levelCount(image, range);
2309 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
2324 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
2350 const VkImageSubresourceRange *range, uint32_t value)
2357 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
2358 uint32_t level_count = radv_get_levelCount(image, range);
2374 VkImageSubresourceRange range = {
2388 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range, cond_val);
2399 VkImageSubresourceRange range = {
2408 assert(radv_htile_enabled(image, range.baseMipLevel));
2410 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range, ds_clear_value, aspects);
2471 const VkImageSubresourceRange *range, bool value)
2477 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2478 uint32_t level_count = radv_get_levelCount(image, range);
2498 const VkImageSubresourceRange *range, bool value)
2504 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2505 uint32_t level_count = radv_get_levelCount(image, range);
2508 assert(radv_dcc_enabled(image, range->baseMipLevel));
2555 const VkImageSubresourceRange *range, uint32_t color_values[2])
2558 uint32_t level_count = radv_get_levelCount(image, range);
2561 assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel));
2564 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2590 VkImageSubresourceRange range = {
2606 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
4609 VkImageSubresourceRange range;
4610 range.aspectMask = view->vk.aspects;
4611 range.baseMipLevel = view->vk.base_mip_level;
4612 range.levelCount = 1;
4613 range.baseArrayLayer = view->vk.base_array_layer;
4614 range.layerCount = cmd_buffer->state.framebuffer->layers;
4624 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
4644 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
4646 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4650 att.layout, att.in_render_loop, 0, 0, &range, sample_locs);
4653 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
4657 att.in_render_loop, 0, 0, &range, sample_locs);
4662 att.layout, att.in_render_loop, 0, 0, &range, sample_locs);
5259 struct radv_descriptor_range *range = set->header.dynamic_descriptors + j;
5261 if (!range->va) {
5264 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
5267 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
9216 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
9217 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
9223 const VkImageSubresourceRange *range)
9239 !(range->aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
9246 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
9248 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);
9250 if (radv_image_is_tc_compat_htile(image) && (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT)) {
9256 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
9265 const VkImageSubresourceRange *range,
9270 if (!radv_htile_enabled(image, range->baseMipLevel))
9274 radv_initialize_htile(cmd_buffer, image, range);
9279 radv_initialize_htile(cmd_buffer, image, range);
9287 radv_expand_depth_stencil(cmd_buffer, image, range, sample_locs);
9296 const VkImageSubresourceRange *range, uint32_t value)
9303 return radv_clear_cmask(cmd_buffer, image, range, value);
9308 const VkImageSubresourceRange *range)
9318 return radv_clear_fmask(cmd_buffer, image, range, value);
9323 const VkImageSubresourceRange *range, uint32_t value)
9332 flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
9372 const VkImageSubresourceRange *range)
9389 radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, dst_layout,
9402 flush_bits |= radv_init_cmask(cmd_buffer, image, range, value);
9406 flush_bits |= radv_init_fmask(cmd_buffer, image, range);
9409 if (radv_dcc_enabled(image, range->baseMipLevel)) {
9412 if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9417 flush_bits |= radv_init_dcc(cmd_buffer, image, range, value);
9420 if (radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel)) {
9421 radv_update_fce_metadata(cmd_buffer, image, range, false);
9424 radv_set_color_clear_metadata(cmd_buffer, image, range, color_values);
9459 const VkImageSubresourceRange *range)
9464 !radv_dcc_enabled(image, range->baseMipLevel))
9469 dst_render_loop, src_queue_mask, dst_queue_mask, range);
9476 if (radv_dcc_enabled(image, range->baseMipLevel)) {
9478 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu);
9479 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9481 !radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9483 radv_decompress_dcc(cmd_buffer, image, range);
9485 } else if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9487 !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9489 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
9496 if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9498 !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9500 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
9510 if (radv_dcc_enabled(image, range->baseMipLevel) &&
9517 radv_decompress_dcc(cmd_buffer, image, range);
9522 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
9529 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
9537 uint32_t dst_family_index, const VkImageSubresourceRange *range,
9571 dst_render_loop, src_queue_mask, dst_queue_mask, range,
9575 dst_render_loop, src_queue_mask, dst_queue_mask, range);