Lines Matching defs:info
981 return &shader->info.user_sgprs_locs.shader_data[idx];
1006 struct radv_userdata_locations *locs = &pipeline->shaders[stage]->info.user_sgprs_locs;
1228 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
1583 S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling));
3059 assert(vs_shader->info.vs.dynamic_inputs);
3093 (!vs_shader->info.vs.as_ls || !instance_rate_inputs) &&
3116 key.as_ls = vs_shader->info.vs.as_ls && instance_rate_inputs;
3117 key.is_ngg = vs_shader->info.is_ngg;
3118 key.wave32 = vs_shader->info.wave_size == 32;
3232 if (vs_shader->info.is_ngg || pipeline->base.shaders[MESA_SHADER_GEOMETRY] == vs_shader) {
3238 } else if (vs_shader->info.vs.as_ls) {
3241 } else if (vs_shader->info.vs.as_es) {
3288 struct util_fast_udiv_info info = util_compute_fast_udiv_info(div, 32, 32);
3289 *(inputs++) = info.pre_shift | (info.increment << 8) | (info.post_shift << 16);
3290 *(inputs++) = info.multiplier;
3298 &vs_shader->info.user_sgprs_locs.shader_data[AC_UD_VS_PROLOG_INPUTS];
3314 if (!vs_shader->info.vs.has_prolog)
3557 const uint64_t mask = shader->info.inline_push_constant_mask;
3709 vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
3750 /* Put all the info in for the DGC generation shader in case the VBO gets overridden. */
3812 /* Put all the info in for the DGC generation shader in case the VBO gets overridden.
3907 loc = &pipeline->base.gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
4137 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
4149 if (info->gfx_level == GFX9) {
4152 } else if (info->gfx_level >= GFX7) {
4164 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
4171 if (info->gfx_level < GFX10) {
4193 if (info->gfx_level >= GFX10) {
4222 if (info->gfx_level == GFX10_3 && state->active_pipeline_queries > 0 &&
4230 (info->gfx_level == GFX10_3 &&
4570 if (view->image->info.samples == 1)
4681 const VkRenderPassBeginInfo *info)
4684 vk_find_struct_const(info->pNext, RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
4754 const VkRenderPassBeginInfo *info)
4759 if (info) {
4760 attachment_info = vk_find_struct_const(info->pNext, RENDER_PASS_ATTACHMENT_BEGIN_INFO);
4803 if (clear_aspects && info) {
4804 assert(info->clearValueCount > i);
4805 state->attachments[i].clear_value = info->pClearValues[i];
5540 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.uses_task_rings;
5618 pipeline->shaders[MESA_SHADER_MESH]->info.ms.needs_ms_scratch_ring;
6415 .width = radv_minify(ds_image->info.width, level),
6416 .height = radv_minify(ds_image->info.height, level),
6443 .width = MIN2(fb->width, ds_image->info.width),
6444 .height = MIN2(fb->height, ds_image->info.height),
6578 &pipeline->base.gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
6741 S_00B800_CS_W32_EN(compute_shader->info.wave_size == 32);
6771 const uint32_t xyz_dim_enable = compute_shader->info.cs.uses_grid_size;
6772 const uint32_t draw_id_enable = compute_shader->info.vs.needs_draw_id;
6774 S_00B800_CS_W32_EN(compute_shader->info.wave_size == 32);
6836 const struct radv_draw_info *info, const uint32_t vertex_offset)
6852 radeon_emit(cs, info->first_instance);
6853 state->last_first_instance = info->first_instance;
6858 radv_emit_userdata_vertex(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,
6869 radv_emit_userdata_vertex_internal(cmd_buffer, info, vertex_offset);
6871 radv_emit_userdata_vertex_internal(cmd_buffer, info, vertex_offset);
6872 } else if (uses_baseinstance && info->first_instance != state->last_first_instance) {
6873 radv_emit_userdata_vertex_internal(cmd_buffer, info, vertex_offset);
6984 const struct radv_draw_info *info,
7000 radv_emit_userdata_vertex(cmd_buffer, info, *vertexOffset);
7039 radv_emit_userdata_vertex(cmd_buffer, info, draw->vertexOffset);
7071 radv_emit_userdata_vertex(cmd_buffer, info, *vertexOffset);
7103 radv_emit_userdata_vertex(cmd_buffer, info, draw->vertexOffset);
7125 radv_emit_direct_draw_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,
7136 radv_emit_userdata_vertex(cmd_buffer, info, draw->firstVertex);
7215 const struct radv_draw_info *info, uint64_t nv_ib_va,
7225 radv_buffer_get_va(info->indirect->bo) + info->indirect->offset + info->indirect_offset;
7226 const uint64_t count_va = !info->count_buffer
7228 : radv_buffer_get_va(info->count_buffer->bo) +
7229 info->count_buffer->offset + info->count_buffer_offset;
7233 radv_cs_add_buffer(ws, cmd_buffer->ace_internal.cs, info->count_buffer->bo);
7267 radv_cs_add_buffer(ws, cmd_buffer->ace_internal.cs, info->indirect->bo);
7292 radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(cmd_buffer, va, info->count,
7293 count_va, info->stride);
7298 radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(cmd_buffer, va, info->count,
7299 count_va, info->stride);
7319 const struct radv_draw_info *info)
7325 radv_buffer_get_va(info->indirect->bo) + info->indirect->offset + info->indirect_offset;
7326 const uint64_t count_va = info->count_buffer
7327 ? radv_buffer_get_va(info->count_buffer->bo) +
7328 info->count_buffer->offset + info->count_buffer_offset
7331 radv_cs_add_buffer(ws, cs, info->indirect->bo);
7338 if (info->count_buffer) {
7339 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
7343 radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, count_va,
7344 info->stride);
7350 radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, count_va,
7351 info->stride);
7374 const struct radv_draw_info *info)
7381 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
7399 if (info->indexed && state->dynamic.primitive_restart_enable &&
7510 assert(v->info.has_ngg_culling == nggc_supported);
7514 const int8_t nggc_sgpr_idx = v->info.user_sgprs_locs.shader_data[AC_UD_NGG_CULLING_SETTINGS].sgpr_idx;
7547 const int8_t vp_sgpr_idx = v->info.user_sgprs_locs.shader_data[AC_UD_NGG_VIEWPORT].sgpr_idx;
7574 rsrc2 = (rsrc2 & C_00B22C_LDS_SIZE) | S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling);
7591 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,
7602 radv_emit_ngg_culling_state(cmd_buffer, info);
7610 late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info);
7615 if (info->indexed) {
7617 radv_emit_index_buffer(cmd_buffer, info->indirect);
7648 radv_emit_draw_registers(cmd_buffer, info);
7656 radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info, uint32_t drawCount)
7665 if (likely(!info->indirect)) {
7670 if (unlikely(!info->instance_count))
7674 if (unlikely(!info->count && !info->strmout_buffer))
7695 radv_emit_all_graphics_states(cmd_buffer, info, pipeline_is_dirty);
7715 radv_emit_all_graphics_states(cmd_buffer, info, pipeline_is_dirty);
7719 if (likely(!info->indirect)) {
7723 if (state->last_num_instances != info->instance_count) {
7725 radeon_emit(cs, info->instance_count);
7726 state->last_num_instances = info->instance_count;
7735 radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,
7746 const bool gfx_result = radv_before_draw(cmd_buffer, info, drawCount);
7757 if (!info->count || !gfx_result)
7979 struct radv_draw_info info;
7981 info.count = vertexCount;
7982 info.instance_count = instanceCount;
7983 info.first_instance = firstInstance;
7984 info.strmout_buffer = NULL;
7985 info.indirect = NULL;
7986 info.indexed = false;
7988 if (!radv_before_draw(cmd_buffer, &info, 1))
7991 radv_emit_direct_draw_packets(cmd_buffer, &info, 1, &minfo, 0, 0);
8000 struct radv_draw_info info;
8005 info.count = pVertexInfo->vertexCount;
8006 info.instance_count = instanceCount;
8007 info.first_instance = firstInstance;
8008 info.strmout_buffer = NULL;
8009 info.indirect = NULL;
8010 info.indexed = false;
8012 if (!radv_before_draw(cmd_buffer, &info, drawCount))
8014 radv_emit_direct_draw_packets(cmd_buffer, &info, drawCount, pVertexInfo, 0, stride);
8023 struct radv_draw_info info;
8025 info.indexed = true;
8026 info.count = indexCount;
8027 info.instance_count = instanceCount;
8028 info.first_instance = firstInstance;
8029 info.strmout_buffer = NULL;
8030 info.indirect = NULL;
8032 if (!radv_before_draw(cmd_buffer, &info, 1))
8035 radv_emit_draw_packets_indexed(cmd_buffer, &info, 1, &minfo, 0, NULL);
8044 struct radv_draw_info info;
8050 info.indexed = true;
8051 info.count = minfo->indexCount;
8052 info.instance_count = instanceCount;
8053 info.first_instance = firstInstance;
8054 info.strmout_buffer = NULL;
8055 info.indirect = NULL;
8057 if (!radv_before_draw(cmd_buffer, &info, drawCount))
8059 radv_emit_draw_packets_indexed(cmd_buffer, &info, drawCount, pIndexInfo, stride, pVertexOffset);
8069 struct radv_draw_info info;
8071 info.count = drawCount;
8072 info.indirect = buffer;
8073 info.indirect_offset = offset;
8074 info.stride = stride;
8075 info.strmout_buffer = NULL;
8076 info.count_buffer = NULL;
8077 info.indexed = false;
8078 info.instance_count = 0;
8080 if (!radv_before_draw(cmd_buffer, &info, 1))
8082 radv_emit_indirect_draw_packets(cmd_buffer, &info);
8092 struct radv_draw_info info;
8094 info.indexed = true;
8095 info.count = drawCount;
8096 info.indirect = buffer;
8097 info.indirect_offset = offset;
8098 info.stride = stride;
8099 info.count_buffer = NULL;
8100 info.strmout_buffer = NULL;
8101 info.instance_count = 0;
8103 if (!radv_before_draw(cmd_buffer, &info, 1))
8105 radv_emit_indirect_draw_packets(cmd_buffer, &info);
8117 struct radv_draw_info info;
8119 info.count = maxDrawCount;
8120 info.indirect = buffer;
8121 info.indirect_offset = offset;
8122 info.count_buffer = count_buffer;
8123 info.count_buffer_offset = countBufferOffset;
8124 info.stride = stride;
8125 info.strmout_buffer = NULL;
8126 info.indexed = false;
8127 info.instance_count = 0;
8129 if (!radv_before_draw(cmd_buffer, &info, 1))
8131 radv_emit_indirect_draw_packets(cmd_buffer, &info);
8144 struct radv_draw_info info;
8146 info.indexed = true;
8147 info.count = maxDrawCount;
8148 info.indirect = buffer;
8149 info.indirect_offset = offset;
8150 info.count_buffer = count_buffer;
8151 info.count_buffer_offset = countBufferOffset;
8152 info.stride = stride;
8153 info.strmout_buffer = NULL;
8154 info.instance_count = 0;
8156 if (!radv_before_draw(cmd_buffer, &info, 1))
8158 radv_emit_indirect_draw_packets(cmd_buffer, &info);
8167 struct radv_draw_info info;
8169 info.count = taskCount;
8170 info.instance_count = 1;
8171 info.first_instance = 0;
8172 info.stride = 0;
8173 info.indexed = false;
8174 info.strmout_buffer = NULL;
8175 info.count_buffer = NULL;
8176 info.indirect = NULL;
8178 if (!radv_before_taskmesh_draw(cmd_buffer, &info, 1))
8198 struct radv_draw_info info;
8200 info.indirect = buffer;
8201 info.indirect_offset = offset;
8202 info.stride = stride;
8203 info.count = drawCount;
8204 info.strmout_buffer = NULL;
8205 info.count_buffer = NULL;
8206 info.indexed = false;
8207 info.instance_count = 0;
8209 if (!radv_before_taskmesh_draw(cmd_buffer, &info, drawCount))
8231 info.indirect = &buf;
8232 info.indirect_offset = 0;
8233 info.stride = sizeof(VkDispatchIndirectCommand);
8235 radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info, nv_ib_va, nv_ib_stride);
8239 info.indirect = &buf;
8240 info.indirect_offset = 0;
8241 info.stride = sizeof(VkDrawIndirectCommand);
8243 radv_emit_indirect_draw_packets(cmd_buffer, &info);
8260 struct radv_draw_info info;
8262 info.indirect = buffer;
8263 info.indirect_offset = offset;
8264 info.stride = stride;
8265 info.count = maxDrawCount;
8266 info.strmout_buffer = NULL;
8267 info.count_buffer = count_buffer;
8268 info.count_buffer_offset = countBufferOffset;
8269 info.indexed = false;
8270 info.instance_count = 0;
8272 if (!radv_before_taskmesh_draw(cmd_buffer, &info, maxDrawCount))
8280 info.indirect = &buf;
8281 info.indirect_offset = 0;
8282 info.stride = sizeof(VkDispatchIndirectCommand);
8284 radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info, nv_ib_va, nv_ib_stride);
8288 info.indirect = &buf;
8289 info.indirect_offset = 0;
8290 info.stride = sizeof(VkDrawIndirectCommand);
8292 radv_emit_indirect_draw_packets(cmd_buffer, &info);
8318 struct radv_draw_info info;
8320 info.count = pGeneratedCommandsInfo->sequencesCount;
8321 info.indirect = prep_buffer; /* We're not really going use it this way, but a good signal
8323 info.indirect_offset = 0;
8324 info.stride = 0;
8325 info.strmout_buffer = NULL;
8326 info.count_buffer = NULL;
8327 info.indexed = layout->indexed;
8328 info.instance_count = 0;
8330 if (!radv_before_draw(cmd_buffer, &info, 1))
8405 const struct radv_dispatch_info *info)
8414 radv_describe_dispatch(cmd_buffer, info->blocks[0], info->blocks[1], info->blocks[2]);
8420 if (compute_shader->info.wave_size == 32) {
8425 if (info->va) {
8426 if (info->indirect)
8427 radv_cs_add_buffer(ws, cs, info->indirect);
8429 if (info->unaligned) {
8431 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
8432 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
8433 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
8444 radeon_emit(cs, info->va);
8445 radeon_emit(cs, info->va >> 32);
8449 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, reg, info->va, true);
8458 radeon_emit(cs, info->va);
8459 radeon_emit(cs, info->va >> 32);
8464 radeon_emit(cs, info->va);
8465 radeon_emit(cs, info->va >> 32);
8472 unsigned blocks[3] = {info->blocks[0], info->blocks[1], info->blocks[2]};
8473 unsigned offsets[3] = {info->offsets[0], info->offsets[1], info->offsets[2]};
8475 if (info->unaligned) {
8476 unsigned *cs_block_size = compute_shader->info.cs.block_size;
8569 radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info,
8595 radv_emit_dispatch_packets(cmd_buffer, pipeline, info);
8618 radv_emit_dispatch_packets(cmd_buffer, pipeline, info);
8641 radv_compute_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info)
8643 radv_dispatch(cmd_buffer, info, cmd_buffer->state.compute_pipeline,
8652 struct radv_dispatch_info info = {0};
8654 info.blocks[0] = x;
8655 info.blocks[1] = y;
8656 info.blocks[2] = z;
8658 info.offsets[0] = base_x;
8659 info.offsets[1] = base_y;
8660 info.offsets[2] = base_z;
8661 radv_compute_dispatch(cmd_buffer, &info);
8675 struct radv_dispatch_info info = {0};
8677 info.indirect = buffer->bo;
8678 info.va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
8680 radv_compute_dispatch(cmd_buffer, &info);
8686 struct radv_dispatch_info info = {0};
8688 info.blocks[0] = x;
8689 info.blocks[1] = y;
8690 info.blocks[2] = z;
8691 info.unaligned = 1;
8693 radv_compute_dispatch(cmd_buffer, &info);
8699 struct radv_dispatch_info info = {0};
8701 info.indirect = bo;
8702 info.va = va;
8704 radv_compute_dispatch(cmd_buffer, &info);
8720 struct radv_dispatch_info info = {0};
8721 info.unaligned = true;
8747 info.blocks[0] = tables->width;
8748 info.blocks[1] = tables->height;
8749 info.blocks[2] = tables->depth;
8751 info.va = launch_size_va;
8767 radv_dispatch(cmd_buffer, &info, pipeline, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR);
8847 wave_size = cmd_buffer->state.rt_pipeline->base.shaders[MESA_SHADER_COMPUTE]->info.wave_size;
8928 const VkRenderingAttachmentInfo *info = &pRenderingInfo->pColorAttachments[i];
8929 RADV_FROM_HANDLE(radv_image_view, iview, info->imageView);
8932 .layout = info->imageLayout,
8935 iviews[att_count] = info->imageView;
8936 clear_values[att_count] = info->clearValue;
8942 att->samples = iview->image->info.samples;
8943 att->loadOp = info->loadOp;
8944 att->storeOp = info->storeOp;
8945 att->initialLayout = info->imageLayout;
8946 att->finalLayout = info->imageLayout;
8954 if (info->resolveMode != VK_RESOLVE_MODE_NONE &&
8956 RADV_FROM_HANDLE(radv_image_view, resolve_iview, info->resolveImageView);
8960 .layout = info->resolveImageLayout,
8963 iviews[att_count] = info->resolveImageView;
8969 att->samples = resolve_iview->image->info.samples;
8972 att->initialLayout = info->resolveImageLayout;
8973 att->finalLayout = info->resolveImageLayout;
9004 att->samples = iview->image->info.samples;
9067 att->samples = resolve_iview->image->info.samples;
9121 att->samples = iview->image->info.samples;
9311 uint32_t log2_samples = util_logbase2(image->info.samples);
9343 dcc_level->dcc_slice_fast_clear_size * image->info.array_size;
9397 uint32_t log2_samples = util_logbase2(image->info.samples);
9914 /* Store conditional rendering user info. */
9932 /* Reset conditional rendering user info. */
9993 enabled_stream_buffers_mask = pipeline->streamout_shader->info.so.enabled_stream_buffers_mask;
10073 struct radv_shader_info *info = &pipeline->streamout_shader->info;
10091 radeon_emit(cs, info->so.strides[i]); /* VTX_STRIDE (in DW) */
10319 struct radv_draw_info info;
10321 info.count = 0;
10322 info.instance_count = instanceCount;
10323 info.first_instance = firstInstance;
10324 info.strmout_buffer = counterBuffer;
10325 info.strmout_buffer_offset = counterBufferOffset;
10326 info.stride = vertexStride;
10327 info.indexed = false;
10328 info.indirect = NULL;
10330 if (!radv_before_draw(cmd_buffer, &info, 1))
10333 radv_emit_direct_draw_packets(cmd_buffer, &info, 1, &minfo, S_0287F0_USE_OPAQUE(1), 0);