Lines Matching defs:index
1978 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
2014 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C6C_CB_COLOR0_VIEW + index * 0x3c, 4);
2020 radeon_set_context_reg(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, cb->cb_color_base);
2021 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->cb_color_base >> 32);
2022 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
2023 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4, cb->cb_dcc_base >> 32);
2024 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4, cb->cb_color_attrib2);
2025 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4, cb->cb_color_attrib3);
2027 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
2040 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
2042 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
2044 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
2046 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
2048 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
2050 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
2052 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
2055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
2068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
2072 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
2075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
2089 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c,
2902 /* With indirect generated commands the index buffer bind may be part of the
2989 * - index of first instanced attribute
3076 u_foreach_bit (index, cmd_buffer->state.vbo_misaligned_mask_invalid & attribute_mask) {
3077 uint8_t binding = state->bindings[index];
3080 uint8_t req = state->format_align_req_minus_1[index];
3082 VkDeviceSize offset = vb->offset + state->offsets[index];
3084 misaligned_mask |= BITFIELD_BIT(index);
3100 unsigned index = radv_instance_rate_prolog_index(num_attributes, instance_rate_inputs);
3101 prolog = device->instance_rate_vs_prologs[index];
3147 u_foreach_bit(index, misaligned_mask) formats[num_formats++] = state->formats[index];
3278 u_foreach_bit(index, nontrivial_divisors)
3280 uint32_t div = state->divisors[index];
3794 /* If attrib_offset>stride, then the compiler will increase the vertex index by
3836 * - 1: index >= NUM_RECORDS (Structured)
4027 /* Un-set the SGPR index so we know to re-emit it later. */
4128 unreachable("invalid index type");
4703 * index attachmentIndex was not created with
5156 unreachable("invalid index type");
5172 unreachable("invalid index type");
6559 unsigned stage, unsigned index)
6565 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, index);
6569 radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
6574 radv_emit_view_index_per_stage(cmd_buffer->cs, pipeline, stage, index);
6581 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
6586 index);
6660 * The starting address "index_va" may point anywhere within the index buffer. The number of
6661 * indexes allocated in the index buffer *past that point* is specified by "max_index_count".
7004 /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
7028 /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
7075 /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
7096 /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
7488 * - Dirty pipeline: SGPR index may have changed (we have to re-emit if changed).
9720 /* Flags that only require a post-index-fetch event. */
9748 /* Sync ME because PFP reads index and indirect buffers. */