Lines Matching defs:image
58 struct radv_image *image, VkImageLayout src_layout,
1985 struct radv_image *image = iview->image;
1988 cmd_buffer->device, image, iview->vk.base_mip_level, layout, in_render_loop,
1989 radv_image_queue_family_mask(image, cmd_buffer->qf,
1999 cmd_buffer->device, image, layout,
2000 radv_image_queue_family_mask(image, cmd_buffer->qf,
2005 if (radv_image_is_tc_compat_cmask(image) && (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
2104 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
2113 const struct radv_image *image = iview->image;
2118 !radv_image_is_tc_compat_htile(image))
2122 cmd_buffer->device, image, layout, in_render_loop,
2123 radv_image_queue_family_mask(image, cmd_buffer->qf,
2141 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->vk.base_mip_level);
2157 const struct radv_image *image = iview->image;
2163 cmd_buffer->device, image, layout, in_render_loop,
2164 radv_image_queue_family_mask(image, cmd_buffer->qf,
2249 * Update the fast clear depth/stencil values if the image is bound as a
2258 const struct radv_image *image = iview->image;
2269 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2298 * Set the clear depth/stencil values to the image's metadata.
2301 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2306 uint32_t level_count = radv_get_levelCount(image, range);
2309 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
2324 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
2346 * Update the TC-compat metadata value for this image.
2349 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2357 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
2358 uint32_t level_count = radv_get_levelCount(image, range);
2388 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range, cond_val);
2392 * Update the clear depth/stencil values for this image.
2406 struct radv_image *image = iview->image;
2408 assert(radv_htile_enabled(image, range.baseMipLevel));
2410 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range, ds_clear_value, aspects);
2412 if (radv_image_is_tc_compat_htile(image) && (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
2420 * Load the clear depth/stencil values from the image's metadata.
2426 const struct radv_image *image = iview->image;
2427 VkImageAspectFlags aspects = vk_format_aspects(image->vk.format);
2428 uint64_t va = radv_get_ds_clear_value_va(image, iview->vk.base_mip_level);
2431 assert(radv_image_has_htile(image));
2470 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2473 if (!image->fce_pred_offset)
2477 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2478 uint32_t level_count = radv_get_levelCount(image, range);
2497 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2500 if (image->dcc_pred_offset == 0)
2504 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2505 uint32_t level_count = radv_get_levelCount(image, range);
2508 assert(radv_dcc_enabled(image, range->baseMipLevel));
2523 * Update the fast clear color values if the image is bound as a color buffer.
2526 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2540 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2551 * Set the clear color values to the image's metadata.
2554 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2558 uint32_t level_count = radv_get_levelCount(image, range);
2561 assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel));
2563 if (radv_image_has_clear_value(image)) {
2564 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2582 * Update the clear color values for this image.
2589 struct radv_image *image = iview->image;
2598 assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, iview->vk.base_mip_level));
2601 * mode because the hardware gets the value from the image directly.
2603 if (iview->image->support_comp_to_single)
2606 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2608 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx, color_values);
2612 * Load the clear color values from the image's metadata.
2619 struct radv_image *image = iview->image;
2621 if (!radv_image_has_cmask(image) && !radv_dcc_enabled(image, iview->vk.base_mip_level))
2624 if (iview->image->support_comp_to_single)
2627 if (!radv_image_has_clear_value(image)) {
2629 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx, color_values);
2633 uint64_t va = radv_image_get_fast_clear_va(image, iview->vk.base_mip_level);
2657 * broken if the CB caches data of multiple mips of the same image at the
2683 if ((radv_image_has_CB_metadata(iview->image) ||
2684 radv_dcc_enabled(iview->image, iview->vk.base_mip_level) ||
2685 radv_dcc_enabled(iview->image, cmd_buffer->state.cb_mip[i])) &&
2730 if (!device->vrs.image) {
2741 return device->vrs.image;
2766 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bindings[0].bo);
2771 if (iview->image->disjoint && iview->vk.aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2772 for (uint32_t plane_id = 0; plane_id < iview->image->plane_count; plane_id++) {
2774 iview->image->bindings[plane_id].bo);
2777 uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0;
2779 iview->image->bindings[plane_id].bo);
2788 iview->image->dcc_sign_reinterpret) {
2806 cmd_buffer->state.attachments[idx].iview->image->bindings[0].bo);
2812 cmd_buffer->device, iview->image, layout, in_render_loop,
2813 radv_image_queue_family_mask(iview->image, cmd_buffer->qf,
2826 struct radv_image *image = cmd_buffer->device->vrs.image;
2833 .image = radv_image_to_handle(image),
2834 .viewType = radv_meta_get_view_type(image),
2835 .format = image->vk.format,
2847 radv_initialise_vrs_surface(image, htile_buffer, &ds);
4322 * the image/buffer it often devolves to just VRAM/GTT anyway.
4331 const struct radv_image *image)
4334 bool image_is_coherent = image ? image->l2_coherent : false;
4337 if (image) {
4338 if (!radv_image_has_CB_metadata(image))
4340 if (!radv_image_has_htile(image))
4352 if (image && !(image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
4353 if (vk_format_is_depth_or_stencil(image->vk.format)) {
4408 const struct radv_image *image)
4413 bool image_is_coherent = image ? image->l2_coherent : false;
4415 if (image) {
4416 if (!(image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
4421 if (!radv_image_has_CB_metadata(image))
4423 if (!radv_image_has_htile(image))
4472 if (!cmd_buffer->device->physical_device->use_llvm && !image)
4534 radv_src_access_flush(cmd_buffer, barrier->src_access_mask, iview->image);
4543 radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask, iview->image);
4570 if (view->image->info.samples == 1)
4618 * performed a fast color/depth clear to the whole image
4620 * decompress the image correctly (if needed), we have to
4647 radv_handle_image_transition(cmd_buffer, view->image,
4655 cmd_buffer, view->image, cmd_buffer->state.attachments[idx].current_stencil_layout,
4659 radv_handle_image_transition(cmd_buffer, view->image,
4696 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
4698 assert(vk_format_is_depth_or_stencil(image->vk.format));
4702 * "If the image referenced by the framebuffer attachment at
4708 if (!(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
6411 struct radv_image *ds_image = ds_iview->image;
6428 radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, &htile_buffer, true);
6448 radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, htile_buffer, false);
6471 if (!cmd_buffer->state.attachments[a].iview->image->l2_coherent) {
6478 .iview->image->l2_coherent)
8942 att->samples = iview->image->info.samples;
8969 att->samples = resolve_iview->image->info.samples;
9004 att->samples = iview->image->info.samples;
9067 att->samples = resolve_iview->image->info.samples;
9121 att->samples = iview->image->info.samples;
9222 radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9226 uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
9236 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, image);
9238 if (image->planes[0].surface.has_stencil &&
9243 state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image);
9246 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
9248 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);
9250 if (radv_image_is_tc_compat_htile(image) && (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT)) {
9256 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
9261 radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9270 if (!radv_htile_enabled(image, range->baseMipLevel))
9274 radv_initialize_htile(cmd_buffer, image, range);
9275 } else if (!radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop,
9277 radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop,
9279 radv_initialize_htile(cmd_buffer, image, range);
9280 } else if (radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop,
9282 !radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop,
9287 radv_expand_depth_stencil(cmd_buffer, image, range, sample_locs);
9295 radv_init_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9303 return radv_clear_cmask(cmd_buffer, image, range, value);
9307 radv_init_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9311 uint32_t log2_samples = util_logbase2(image->info.samples);
9318 return radv_clear_fmask(cmd_buffer, image, range, value);
9322 radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9332 flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
9340 for (unsigned i = 0; i < image->planes[0].surface.num_meta_levels; i++) {
9341 struct legacy_surf_dcc_level *dcc_level = &image->planes[0].surface.u.legacy.color.dcc_level[i];
9343 dcc_level->dcc_slice_fast_clear_size * image->info.array_size;
9352 if (size != image->planes[0].surface.meta_size) {
9353 flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
9354 radv_buffer_get_va(image->bindings[0].bo) +
9355 image->bindings[0].offset +
9356 image->planes[0].surface.meta_offset + size,
9357 image->planes[0].surface.meta_size - size, 0xffffffff);
9365 * Initialize DCC/FMASK/CMASK metadata for a color image.
9368 radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9380 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, image);
9382 if (radv_image_has_cmask(image)) {
9387 if (radv_image_is_tc_compat_cmask(image) ||
9388 (radv_image_has_fmask(image) &&
9389 radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, dst_layout,
9397 uint32_t log2_samples = util_logbase2(image->info.samples);
9402 flush_bits |= radv_init_cmask(cmd_buffer, image, range, value);
9405 if (radv_image_has_fmask(image)) {
9406 flush_bits |= radv_init_fmask(cmd_buffer, image, range);
9409 if (radv_dcc_enabled(image, range->baseMipLevel)) {
9412 if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9417 flush_bits |= radv_init_dcc(cmd_buffer, image, range, value);
9420 if (radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel)) {
9421 radv_update_fce_metadata(cmd_buffer, image, range, false);
9424 radv_set_color_clear_metadata(cmd_buffer, image, range, color_values);
9431 radv_retile_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9434 /* If the image is read-only, we don't have to retile DCC because it can't change. */
9435 if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS))
9441 radv_retile_dcc(cmd_buffer, image);
9445 radv_image_need_retile(const struct radv_image *image)
9447 return image->planes[0].surface.display_dcc_offset &&
9448 image->planes[0].surface.display_dcc_offset != image->planes[0].surface.meta_offset;
9452 * Handle color image transitions for DCC/FMASK/CMASK.
9455 radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9463 if (!radv_image_has_cmask(image) && !radv_image_has_fmask(image) &&
9464 !radv_dcc_enabled(image, range->baseMipLevel))
9468 radv_init_color_image_metadata(cmd_buffer, image, src_layout, src_render_loop, dst_layout,
9471 if (radv_image_need_retile(image))
9472 radv_retile_transition(cmd_buffer, image, src_layout, dst_layout, dst_queue_mask);
9476 if (radv_dcc_enabled(image, range->baseMipLevel)) {
9478 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu);
9479 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9481 !radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9483 radv_decompress_dcc(cmd_buffer, image, range);
9485 } else if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9487 !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9489 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
9493 if (radv_image_need_retile(image))
9494 radv_retile_transition(cmd_buffer, image, src_layout, dst_layout, dst_queue_mask);
9495 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
9496 if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9498 !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9500 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
9506 if (radv_image_has_fmask(image) &&
9507 (image->vk.usage & (VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
9508 radv_layout_fmask_compressed(cmd_buffer->device, image, src_layout, src_queue_mask) &&
9509 !radv_layout_fmask_compressed(cmd_buffer->device, image, dst_layout, dst_queue_mask)) {
9510 if (radv_dcc_enabled(image, range->baseMipLevel) &&
9511 !radv_image_use_dcc_image_stores(cmd_buffer->device, image) && !dcc_decompressed) {
9517 radv_decompress_dcc(cmd_buffer, image, range);
9522 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
9529 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
9534 radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
9542 if (image->exclusive && src_family_index != dst_family_index) {
9562 radv_image_queue_family_mask(image, src_qf, cmd_buffer->qf);
9564 radv_image_queue_family_mask(image, dst_qf, cmd_buffer->qf);
9569 if (vk_format_has_depth(image->vk.format)) {
9570 radv_handle_depth_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout,
9574 radv_handle_color_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout,
9583 * buffer (or a MSAA image using FMASK). Note that updating a buffer is considered a clear
9626 RADV_FROM_HANDLE(radv_image, image, dep_info->pImageMemoryBarriers[i].image);
9630 radv_src_access_flush(cmd_buffer, dep_info->pImageMemoryBarriers[i].srcAccessMask, image);
9633 radv_dst_access_flush(cmd_buffer, dep_info->pImageMemoryBarriers[i].dstAccessMask, image);
9654 RADV_FROM_HANDLE(radv_image, image, dep_info->pImageMemoryBarriers[i].image);
9661 assert(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
9670 cmd_buffer, image, dep_info->pImageMemoryBarriers[i].oldLayout,