Lines Matching defs:device
356 cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
381 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
408 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->device->ws, up->upload_bo);
414 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->device->ws, cmd_buffer->upload.upload_bo);
417 radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device),
423 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
425 cmd_buffer->device->ws->cs_destroy(cmd_buffer->ace_internal.cs);
431 vk_descriptor_set_layout_unref(&cmd_buffer->device->vk, &set->layout->vk);
442 radv_create_cmd_buffer(struct radv_device *device, struct radv_cmd_pool *pool,
450 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
459 cmd_buffer->device = device;
463 cmd_buffer->qf = vk_queue_to_radv(device->physical_device, pool->vk.queue_family_index);
465 ring = radv_queue_family_to_ring(device->physical_device, cmd_buffer->qf);
467 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
470 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
473 vk_object_base_init(&device->vk, &cmd_buffer->meta_push_descriptors.base,
479 vk_object_base_init(&device->vk, &cmd_buffer->descriptors[i].push_set.set.base,
494 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
496 cmd_buffer->device->ws->cs_reset(cmd_buffer->ace_internal.cs);
500 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->device->ws, up->upload_bo);
506 radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device),
529 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->upload.upload_bo);
543 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
553 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 &&
555 unsigned num_db = cmd_buffer->device->physical_device->rad_info.max_render_backends;
567 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
589 struct radv_device *device = cmd_buffer->device;
595 device->ws->buffer_create(device->ws, new_size, 4096, device->ws->cs_domain(device->ws),
605 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
611 device->ws->buffer_destroy(device->ws, bo);
622 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
638 struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info;
679 struct radv_device *device = cmd_buffer->device;
683 va = radv_buffer_get_va(device->trace_bo);
690 radeon_check_space(cmd_buffer->device->ws, cs, 2);
731 si_cs_emit_cache_flush(ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0,
774 cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
788 radeon_check_space(cmd_buffer->device->ws, ace_cs, 7);
799 struct radv_device *device = cmd_buffer->device;
800 struct radeon_cmdbuf *ace_cs = device->ws->cs_create(device->ws, AMD_IP_COMPUTE);
813 struct radv_device *device = cmd_buffer->device;
828 si_cs_emit_write_event_eop(ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
843 device->ws->cs_add_buffers(ace_cs, cmd_buffer->cs);
844 return device->ws->cs_finalize(ace_cs);
850 if (unlikely(cmd_buffer->device->thread_trace.bo)) {
855 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
859 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
863 cmd_buffer->device->physical_device->rad_info.gfx_level,
872 cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0,
877 if (unlikely(cmd_buffer->device->trace_bo))
884 struct radv_device *device = cmd_buffer->device;
889 va = radv_buffer_get_va(device->trace_bo);
891 ring = radv_queue_family_to_ring(device->physical_device, cmd_buffer->qf);
914 struct radv_device *device = cmd_buffer->device;
918 va = radv_buffer_get_va(device->trace_bo);
930 struct radv_device *device = cmd_buffer->device;
934 va = radv_buffer_get_va(device->trace_bo);
962 struct radv_device *device = cmd_buffer->device;
965 va = radv_buffer_get_va(device->trace_bo) + 40;
985 radv_emit_userdata_address(struct radv_device *device, struct radeon_cmdbuf *cs,
996 radv_emit_shader_pointer(device, cs, base_reg + loc->sgpr_idx * 4, va, false);
1000 radv_emit_descriptor_pointers(struct radv_device *device, struct radeon_cmdbuf *cs,
1023 radv_emit_shader_pointer_body(device, cs, set->header.va, true);
1206 radv_emit_inline_push_consts(struct radv_device *device, struct radeon_cmdbuf *cs,
1215 radeon_check_space(device->ws, cs, 2 + loc->num_sgprs);
1245 if (pipeline->base.device->physical_device->rad_info.gfx_level < GFX9)
1254 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
1255 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
1256 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
1257 cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
1324 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1348 format = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11
1352 has_alpha = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11
1490 if (!cmd_buffer->device->pbb_allowed)
1494 radv_get_binning_settings(cmd_buffer->device->physical_device);
1597 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.slab_bo);
1599 if (unlikely(cmd_buffer->device->trace_bo))
1811 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
1812 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cmd_buffer->cs,
1873 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3);
1931 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1934 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1982 bool is_vi = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8;
1988 cmd_buffer->device, image, iview->vk.base_mip_level, layout, in_render_loop,
1991 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1999 cmd_buffer->device, image, layout,
2013 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
2026 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
2054 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
2117 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
2122 cmd_buffer->device, image, layout, in_render_loop,
2130 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
2163 cmd_buffer->device, image, layout, in_render_loop,
2170 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3 &&
2178 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
2182 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
2201 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
2354 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
2444 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2636 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2670 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9)
2706 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9)
2728 struct radv_device *device = cmd_buffer->device;
2730 if (!device->vrs.image) {
2734 result = radv_device_init_vrs_state(device);
2741 return device->vrs.image;
2751 unsigned color_invalid = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11
2766 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bindings[0].bo);
2773 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2778 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2787 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 &&
2805 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2812 cmd_buffer->device, iview->image, layout, in_render_loop,
2825 struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer;
2826 struct radv_image *image = cmd_buffer->device->vrs.image;
2830 radv_image_view_init(&iview, cmd_buffer->device,
2849 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, htile_buffer->bo);
2860 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX11)
2863 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9)
2875 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8) {
2877 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2878 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
2881 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
2913 !cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug) {
2934 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
2950 cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10 && has_perfect_queries;
2952 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
3063 struct radv_device *device = cmd_buffer->device;
3073 assert(device->physical_device->rad_info.gfx_level == GFX6 ||
3074 device->physical_device->rad_info.gfx_level >= GFX10);
3096 prolog = device->simple_vs_prologs[num_attributes - 1];
3101 prolog = device->instance_rate_vs_prologs[index];
3176 u_rwlock_rdlock(&device->vs_prologs_lock);
3178 _mesa_hash_table_search_pre_hashed(device->vs_prologs, hash, key_words);
3179 u_rwlock_rdunlock(&device->vs_prologs_lock);
3182 u_rwlock_wrlock(&device->vs_prologs_lock);
3183 prolog_entry = _mesa_hash_table_search_pre_hashed(device->vs_prologs, hash, key_words);
3185 u_rwlock_wrunlock(&device->vs_prologs_lock);
3189 prolog = radv_create_vs_prolog(device, &key);
3192 radv_shader_part_destroy(device, prolog);
3194 u_rwlock_wrunlock(&device->vs_prologs_lock);
3198 _mesa_hash_table_insert_pre_hashed(device->vs_prologs, hash, key2, prolog);
3200 u_rwlock_wrunlock(&device->vs_prologs_lock);
3215 enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
3253 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, prolog->bo);
3302 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
3329 if (unlikely(cmd_buffer->device->trace_bo))
3343 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
3448 struct radv_device *device = cmd_buffer->device;
3456 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_VERTEX,
3460 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_FRAGMENT,
3464 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_MESH,
3468 radv_emit_userdata_address(device, cmd_buffer->ace_internal.cs, pipeline, MESA_SHADER_TASK,
3472 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_GEOMETRY,
3476 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_TESS_CTRL,
3480 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_TESS_EVAL,
3483 radv_emit_userdata_address(device, cs, pipeline, MESA_SHADER_COMPUTE,
3494 struct radv_device *device = cmd_buffer->device;
3510 radeon_check_space(device->ws, cs, MAX_SETS * MESA_VULKAN_SHADER_STAGES * 4);
3513 radv_emit_descriptor_pointers(device, cs, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3520 radv_emit_descriptor_pointers(device, cs, pipeline, descriptors_state, stage);
3524 radv_emit_descriptor_pointers(device, cmd_buffer->ace_internal.cs, pipeline,
3534 if (unlikely(cmd_buffer->device->trace_bo))
3547 radv_emit_all_inline_push_consts(struct radv_device *device, struct radeon_cmdbuf *cs,
3564 radv_emit_inline_push_consts(device, cs, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS,
3572 radv_emit_inline_push_consts(device, cs, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS,
3581 struct radv_device *device = cmd_buffer->device;
3615 device, cs, pipeline, stage, (uint32_t *)cmd_buffer->push_constants, &need_push_constants);
3619 radv_emit_all_inline_push_consts(device, cmd_buffer->ace_internal.cs, pipeline,
3638 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MESA_VULKAN_SHADER_STAGES * 4);
3647 radv_emit_userdata_address(device, cs, pipeline, stage, AC_UD_PUSH_CONSTANTS, va);
3654 radv_emit_userdata_address(device, cmd_buffer->ace_internal.cs, pipeline, MESA_SHADER_TASK,
3704 enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
3873 radv_emit_userdata_address(cmd_buffer->device, cmd_buffer->cs, &pipeline->base,
3879 if (unlikely(cmd_buffer->device->trace_bo))
3902 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,
3911 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
3954 if (cmd_buffer->device->physical_device->use_ngg_streamout)
3961 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
3964 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
4020 enum amd_gfx_level gfx_level = pipeline->base.device->physical_device->rad_info.gfx_level;
4037 switch (cmd_buffer->device->force_vrs) {
4137 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
4150 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs,
4164 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
4215 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
4235 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
4236 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs,
4293 can_skip_buffer_l2_flushes(struct radv_device *device)
4295 return device->physical_device->rad_info.gfx_level == GFX9 ||
4296 (device->physical_device->rad_info.gfx_level >= GFX10 &&
4297 !device->physical_device->rad_info.tcc_rb_non_coherent);
4430 can_skip_buffer_l2_flushes(cmd_buffer->device) && !cmd_buffer->state.rb_noncoherent_dirty;
4437 if (!cmd_buffer->device->load_grid_size_from_user_sgpr)
4441 if (cmd_buffer->device->uses_device_generated_commands) {
4444 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9)
4472 if (!cmd_buffer->device->physical_device->use_llvm && !image)
4482 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9)
4822 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
4824 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
4835 RADV_FROM_HANDLE(radv_device, device, _device);
4859 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level, &pCommandBuffers[i]);
4884 radv_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount,
4994 radv_CreateRenderPass2(radv_device_to_handle(cmd_buffer->device), &rp_create_info, NULL, &rp);
5078 if (unlikely(cmd_buffer->device->trace_bo))
5102 enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
5129 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->vertex_binding_buffers[idx]->bo);
5193 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
5200 struct radeon_winsys *ws = cmd_buffer->device->ws;
5207 if (!cmd_buffer->device->use_global_bo_list) {
5228 cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
5271 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
5274 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
5299 vk_descriptor_set_layout_unref(&cmd_buffer->device->vk, &set->header.layout->vk);
5348 radv_cmd_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
5381 radv_cmd_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
5408 radv_cmd_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
5433 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX6)
5445 if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))
5479 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
5499 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.cs.cdw);
5507 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.slab_bo);
5509 if (unlikely(cmd_buffer->device->trace_bo))
5595 if (cmd_buffer->device->physical_device->rad_info.has_vgt_flush_ngg_legacy_bug &&
6063 enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
6102 radv_translate_vertex_format(cmd_buffer->device->physical_device, attrib->format, format_desc,
6158 if (secondary->device->physical_device->rad_info.gfx_level == GFX7 &&
6225 primary->device->ws->cs_execute_secondary(ace_primary, ace_secondary, false);
6238 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs, allow_ib2);
6301 RADV_FROM_HANDLE(radv_device, device, _device);
6305 vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6307 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
6309 VkResult result = vk_command_pool_init(&pool->vk, &device->vk, pCreateInfo, pAllocator);
6311 vk_free2(&device->vk.alloc, pAllocator, pool);
6327 RADV_FROM_HANDLE(radv_device, device, _device);
6344 vk_free2(&device->vk.alloc, pAllocator, pool);
6348 radv_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags)
6364 radv_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags)
6380 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4096);
6425 radv_buffer_init(&htile_buffer, cmd_buffer->device, ds_image->bindings[0].bo, htile_size, htile_offset);
6440 struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer;
6740 const uint32_t dispatch_initiator = cmd_buffer->device->dispatch_initiator_task |
6773 const uint32_t dispatch_initiator = cmd_buffer->device->dispatch_initiator_task |
6996 !uses_drawid && cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10;
7006 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
7030 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
7059 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10) {
7077 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
7098 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
7219 struct radeon_winsys *ws = cmd_buffer->device->ws;
7322 struct radeon_winsys *ws = cmd_buffer->device->ws;
7378 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
7600 if (cmd_buffer->device->physical_device->use_ngg_culling &&
7623 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
7629 if (cmd_buffer->device->force_vrs != RADV_FORCE_VRS_1x1) {
7658 const bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
7663 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4096 + 128 * (drawCount - 1));
7761 struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
7763 struct radeon_winsys *ws = cmd_buffer->device->ws;
7799 const struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info;
7800 bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
7831 struct radeon_winsys *ws = cmd_buffer->device->ws;
7915 struct radeon_winsys *ws = cmd_buffer->device->ws;
8408 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
8409 struct radeon_winsys *ws = cmd_buffer->device->ws;
8421 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10);
8441 if (cmd_buffer->device->load_grid_size_from_user_sgpr) {
8442 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3);
8449 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, reg, info->va, true);
8507 if (cmd_buffer->device->load_grid_size_from_user_sgpr) {
8520 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
8572 bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
8756 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
8763 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
8810 assert(cmd_buffer->device->use_global_bo_list);
8834 assert(cmd_buffer->device->use_global_bo_list);
9146 radv_CreateRenderPass2(radv_device_to_handle(cmd_buffer->device), &rp_create_info, NULL, &rp);
9175 vk_common_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device), &fb_create_info, NULL, &fb);
9177 radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device), rp, NULL);
9208 vk_common_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device),
9210 radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device),
9226 uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
9268 struct radv_device *device = cmd_buffer->device;
9275 } else if (!radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop,
9277 radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop,
9280 } else if (radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop,
9282 !radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop,
9334 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX8) {
9385 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) {
9389 radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, dst_layout,
9412 if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9479 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9481 !radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,
9485 } else if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9487 !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9496 if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9498 !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,
9508 radv_layout_fmask_compressed(cmd_buffer->device, image, src_layout, src_queue_mask) &&
9509 !radv_layout_fmask_compressed(cmd_buffer->device, image, dst_layout, dst_queue_mask)) {
9511 !radv_image_use_dcc_image_stores(cmd_buffer->device, image) && !dcc_decompressed) {
9540 enum radv_queue_family src_qf = vk_queue_to_radv(cmd_buffer->device->physical_device, src_family_index);
9541 enum radv_queue_family dst_qf = vk_queue_to_radv(cmd_buffer->device->physical_device, dst_family_index);
9705 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
9707 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28);
9768 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
9816 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
9818 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
9860 !cmd_buffer->device->physical_device->rad_info.has_32bit_predication) {
9963 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, sb[idx].buffer->bo);
10018 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
10023 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
10036 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
10043 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
10115 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
10140 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10);
10171 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
10194 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
10240 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
10264 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10);
10284 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
10288 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
10302 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
10349 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
10360 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,