Lines Matching refs:operands
186 for (unsigned i = 0; i < std::min<unsigned>(2, instr->operands.size()); i++) {
187 const Operand& op = instr->operands[i];
188 check(op.bytes() <= 4, "SDWA operands must not be larger than 4 bytes", instr.get());
196 if (instr->operands.size() >= 3) {
197 check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
232 if (i >= instr->operands.size() ||
233 (instr->operands[i].hasRegClass() &&
234 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
248 for (unsigned i = 0; i < instr->operands.size(); i++) {
249 if (instr->operands[i].hasRegClass() &&
250 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed())
259 for (unsigned i = 0; i < instr->operands.size(); i++) {
260 if (instr->operands[i].isUndefined()) {
268 check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
270 check(instr->operands[i].isFixed() || instr->operands[i].isTemp() ||
271 instr->operands[i].isConstant(),
287 for (unsigned i = 0; i < instr->operands.size(); i++) {
288 Operand op = instr->operands[i];
332 for (unsigned i = 0; i < instr->operands.size(); i++) {
333 Operand op = instr->operands[i];
351 "Lane select operands of v_permlane must be SGPR or constant",
365 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
387 for (const Operand& op : instr->operands) {
398 for (const Operand& op : instr->operands) {
405 for (const Operand& op : instr->operands) {
411 check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(),
413 check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <=
414 instr->operands[0].bytes(),
417 instr->operands[0].regClass().type() == RegType::sgpr,
421 instr->operands[0].regClass().type() == RegType::vgpr,
424 check(instr->operands[0].isTemp(), "Operand must be a temporary", instr.get());
429 check(size == instr->operands[0].bytes(),
431 if (instr->operands[0].getTemp().type() == RegType::vgpr) {
441 check(instr->definitions.size() == instr->operands.size(),
443 for (unsigned i = 0; i < instr->operands.size(); i++) {
444 check(instr->definitions[i].bytes() == instr->operands[i].bytes(),
446 if (instr->operands[i].isTemp()) {
448 instr->operands[i].regClass().type()) ||
450 instr->operands[i].regClass().type() == RegType::sgpr),
453 instr->operands[i].regClass().is_linear_vgpr(),
462 check(instr->operands.size() == block.logical_preds.size(),
466 for (const Operand& op : instr->operands)
470 for (const Operand& op : instr->operands) {
476 check(instr->operands.size() == block.linear_preds.size(),
480 check(instr->operands[0].isTemp(), "Data operand must be temporary", instr.get());
481 check(instr->operands[1].isConstant(), "Index must be constant", instr.get());
483 check(instr->operands[3].isConstant(), "Sign-extend flag must be constant",
487 instr->operands[0].getTemp().type() == RegType::sgpr,
491 check(instr->operands[0].bytes() == instr->definitions[0].bytes(),
499 unsigned data_bits = instr->operands[0].getTemp().bytes() * 8u;
500 unsigned op_bits = instr->operands[2].constantValue();
513 check(instr->operands[1].constantValue() < comp, "Index must be in-bounds",
518 check(instr->operands.size() > 0 &&
519 instr->operands[0].getTemp().type() == RegType::sgpr &&
520 instr->operands[0].getTemp().size() == 2,
522 for (unsigned i = 1; i < instr->operands.size(); i++) {
523 check(instr->operands[i].getTemp().type() == RegType::vgpr ||
524 instr->operands[i].isUndefined(),
525 "Other operands of p_jump_to_epilog must be VGPRs or undef", instr.get());
531 for (const Operand& op : instr->operands)
533 "All operands of PSEUDO_REDUCTION instructions must be in VGPRs.",
549 if (instr->operands.size() >= 1)
550 check((instr->operands[0].isFixed() && !instr->operands[0].isConstant()) ||
551 (instr->operands[0].isTemp() &&
552 instr->operands[0].regClass().type() == RegType::sgpr),
553 "SMEM operands must be sgpr", instr.get());
554 if (instr->operands.size() >= 2)
555 check(instr->operands[1].isConstant() ||
556 (instr->operands[1].isTemp() &&
557 instr->operands[1].regClass().type() == RegType::sgpr),
566 check(instr->operands.size() > 1, "VMEM instructions must have at least one operand",
568 check(instr->operands[1].hasRegClass() &&
569 instr->operands[1].regClass().type() == RegType::vgpr,
572 instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr,
574 check(instr->operands.size() < 4 ||
575 (instr->operands[3].isTemp() &&
576 instr->operands[3].regClass().type() == RegType::vgpr),
611 check(instr->operands.size() >= 4, "MIMG instructions must have at least 4 operands",
613 check(instr->operands[0].hasRegClass() &&
614 (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
615 "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
616 if (instr->operands[1].hasRegClass())
617 check(instr->operands[1].regClass() == s4,
618 "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
619 if (!instr->operands[2].isUndefined()) {
623 (instr->definitions[0].regClass() == instr->operands[2].regClass() ||
625 "MIMG operands[2] (VDATA) must be the same as definitions[0] for atomics and "
629 check(instr->operands.size() == 4 || program->gfx_level >= GFX10,
631 for (unsigned i = 3; i < instr->operands.size(); i++) {
632 if (instr->operands.size() == 4) {
633 check(instr->operands[i].hasRegClass() &&
634 instr->operands[i].regClass().type() == RegType::vgpr,
635 "MIMG operands[3] (VADDR) must be VGPR", instr.get());
637 check(instr->operands[i].regClass() == v1, "MIMG VADDR must be v1 if NSA is used",
654 for (const Operand& op : instr->operands) {
656 "Only VGPRs are valid DS instruction operands", instr.get());
665 check(instr->operands[i].hasRegClass() &&
666 instr->operands[i].regClass().type() == RegType::vgpr,
671 check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR",
676 instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr,
680 check(instr->operands[0].hasRegClass() &&
681 instr->operands[0].regClass().type() == RegType::vgpr,
683 check(instr->operands[1].hasRegClass() &&
684 instr->operands[1].regClass().type() == RegType::sgpr,
687 check(instr->operands[0].isTemp() || instr->operands[1].isTemp(),
693 check(instr->operands[2].regClass().type() == RegType::vgpr,
791 Operand op = instr->operands[index];
1007 for (unsigned i = 0; i < instr->operands.size(); i++) {
1008 if (instr->operands[i].isTemp() &&
1009 instr->operands[i].getTemp().type() == RegType::sgpr &&
1010 instr->operands[i].isFirstKill())
1011 phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
1016 for (unsigned i = 0; i < instr->operands.size(); i++) {
1017 Operand& op = instr->operands[i];
1087 /* remove killed p_phi sgpr operands */
1109 /* check killed p_phi sgpr operands */
1130 /* don't count phi operands as live-in, since they are actually
1133 for (const Operand& op : instr->operands) {
1151 /* remove killed p_phi operands from regs */
1161 for (const Operand& op : instr->operands) {
1175 for (const Operand& op : instr->operands) {