Lines Matching defs:reg
46 void add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg reg);
49 PhysReg reg;
60 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {}
64 reg = def.physReg();
111 PhysReg reg;
113 PhysReg operator*() const { return reg; }
117 reg.reg_b += 4;
123 reg.reg_b -= 4;
127 bool operator==(PhysRegIterator oth) const { return reg == oth.reg; }
129 bool operator!=(PhysRegIterator oth) const { return reg != oth.reg; }
131 bool operator<(PhysRegIterator oth) const { return reg < oth.reg; }
147 lo_ = PhysReg{lo_.reg() + stride};
156 bool contains(PhysReg reg) const { return lo() <= reg && reg < hi(); }
264 for (PhysReg reg : reg_interval)
265 res += !regs[reg];
345 unsigned get_id(PhysReg reg)
347 return regs[reg] == 0xF0000000 ? subdword_regs[reg][reg.byte()] : regs[reg];
380 print_reg(const RegisterFile& reg_file, PhysReg reg, bool has_adjacent_variable)
382 if (reg_file[reg] == 0xFFFFFFFF) {
384 } else if (reg_file[reg]) {
385 const bool show_subdword_alloc = (reg_file[reg] == 0xF0000000);
397 if (reg_file.subdword_regs.at(reg)[i]) {
456 std::count_if(regs.begin(), regs.end(), [&](auto reg) { return !reg_file[reg]; });
464 PhysReg reg = var.reg;
465 ASSERTED auto inserted = regs_to_vars.emplace(reg, std::make_pair(var.rc.bytes(), id));
478 printf("= %c[%d", reg_char, first_reg.reg() - regs.lo());
480 if (first_reg.reg() != last_reg.reg()) {
482 printf("-%d", last_reg.reg() - regs.lo());
675 add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg reg)
684 if (reg.byte() == 0 && instr_is_16bit(gfx_level, instr->opcode))
689 assert(reg.byte() == 2);
706 if (reg.byte() == 0)
745 adjust_max_used_regs(ra_ctx& ctx, RegClass rc, unsigned reg)
750 assert(reg >= 256);
751 uint16_t hi = reg - 256 + size - 1;
753 } else if (reg + rc.size() <= max_addressible_sgpr) {
754 uint16_t hi = reg + size - 1;
790 // FIXME: ensure that the definition can use this reg
793 ctx.assignments[def.tempId()].reg = def.physReg();
808 ctx.assignments[other.second.tempId()].reg = other.second.physReg();
815 // FIXME: ensure that the operand can use this reg
845 ? (copy.first.physReg() + copy.first.size() <= def_reg.reg())
846 : (def_reg + pc.second.size() <= copy.first.physReg().reg());
975 /* check if also the neighboring reg is free if needed */
1029 (var_a.rc.bytes() == var_b.rc.bytes() && var_a.reg < var_b.reg);
1034 reg_file.clear(var.reg, var.rc);
1045 PhysReg reg = def_reg.lo();
1050 assert(!reg_file.test(reg, instr->operands[i].bytes()));
1051 return {reg, info.rc.is_subdword() || reg.byte() == 0};
1053 reg.reg_b += instr->operands[i].bytes();
1061 if (def_reg.contains(PhysRegInterval{var.reg, info.size})) {
1062 reg = def_reg.lo();
1065 if (reg != var.reg) {
1066 reg.reg_b += instr->operands[i].bytes();
1075 if (!intersects(def_reg, PhysRegInterval{op.reg, op.rc.size()}) &&
1076 reg_file.get_id(op.reg) == instr->operands[i].tempId()) {
1077 Definition pc_def = Definition(reg, info.rc);
1079 return {op.reg, true};
1138 pc_op.setFixed(var.reg);
1214 /* collect variables and block reg file */
1227 pc_op.setFixed(var.reg);
1254 !reg_file.test(PhysReg{op.physReg().reg()}, align(op.bytes() + op.physReg().byte(), 4))) {
1385 PhysReg reg)
1388 if (reg >= PhysReg{512})
1395 if (rc.is_subdword() && reg.byte() % sdw_def_info.first)
1397 if (!rc.is_subdword() && reg.byte())
1400 if (rc.type() == RegType::sgpr && reg % get_stride(rc) != 0)
1403 PhysRegInterval reg_win = {reg, rc.size()};
1408 bool is_m0 = rc == s1 && reg == m0;
1414 test_reg.reg_b = reg.reg_b & ~(sdw_def_info.second - 1);
1418 if (reg_file.test(reg, rc.bytes()))
1485 return ctx.assignments[a.id].reg < ctx.assignments[b.id].reg;
1498 if (next_reg != ctx.assignments[var.id].reg) {
1503 pc_op.setFixed(ctx.assignments[var.id].reg);
1527 PhysReg reg = ctx.assignments[op.tempId()].reg;
1529 if (first.reg() == 512) {
1531 first = reg.advance(i * -4);
1536 if (reg != first.advance(i * 4)) /* not at the best position */
1543 if (first.reg() != 512 && reg_file.test(first.advance(i * 4), 4))
1575 PhysReg reg = ctx.assignments[op.tempId()].reg;
1576 reg.reg_b += (our_offset - their_offset);
1577 if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, reg))
1578 return {reg, true};
1593 PhysReg reg = res.first;
1595 reg.reg_b += our_offset;
1597 if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, reg))
1598 return {reg, true};
1616 PhysReg reg = affinity.reg;
1617 reg.reg_b -= offset;
1618 if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, reg))
1619 return reg;
1629 if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, affinity.reg))
1630 return affinity.reg;
1770 PhysReg reg;
1771 reg.reg_b = j * 4;
1773 for (unsigned byte_idx = 0; byte_idx < MIN2(bytes_left, 4); byte_idx++, reg.reg_b++)
1774 k += reg_file.test(reg, 1);
1895 int reg = ctx.max_used_sgpr;
1896 for (; reg >= 0 && reg_file[PhysReg{(unsigned)reg}]; reg--)
1898 if (reg < 0) {
1899 reg = ctx.max_used_sgpr + 1;
1900 for (; reg < ctx.program->max_reg_demand.sgpr && reg_file[PhysReg{(unsigned)reg}]; reg++)
1902 if (reg == ctx.program->max_reg_demand.sgpr) {
1904 reg = m0;
1908 adjust_max_used_regs(ctx, s1, reg);
1909 instr->pseudo().scratch_sgpr = PhysReg{(unsigned)reg};
1913 operand_can_use_reg(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr, unsigned idx, PhysReg reg,
1917 return instr->operands[idx].physReg() == reg;
1928 return reg == m0;
1932 if (reg.byte()) {
1934 if (reg.byte() % stride)
1940 return reg != scc && reg != exec &&
1941 (reg != m0 || idx == 1 || idx == 3) && /* offset can be m0 */
1942 (reg != vcc || (instr->definitions.empty() && idx == 2) ||
1956 PhysReg src = ctx.assignments[operand.tempId()].reg;
1961 /* check if target reg is blocked, and move away the blocking var */
1997 PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, phi);
2049 return reg;
2073 PhysReg reg = phi->operands[0].physReg();
2075 { return op.isTemp() && (!op.isFixed() || op.physReg() == reg); };
2080 if (!get_reg_specified(ctx, register_file, definition.regClass(), phi, reg))
2083 definition.setFixed(reg);
2099 if (get_reg_specified(ctx, register_file, definition.regClass(), phi, affinity.reg)) {
2100 definition.setFixed(affinity.reg);
2113 PhysReg reg = op.physReg();
2114 if (get_reg_specified(ctx, register_file, definition.regClass(), phi, reg)) {
2115 definition.setFixed(reg);
2192 phi->operands[i].setFixed(ctx.assignments[ops[i].id()].reg);
2232 /* use the assignment from the loop preheader and fix def reg */
2235 loop_header.instructions[0]->definitions[0].setFixed(var.reg);
2257 op.setFixed(ctx.assignments[op.tempId()].reg);
2292 * Reg-to-reg moves (renames) from previous blocks are taken into account and
2317 operand.setFixed(ctx.assignments[operand.tempId()].reg);
2327 register_file.fill(Definition(renamed.id(), var.reg, var.rc));
2342 operand.setFixed(ctx.assignments[operand.tempId()].reg);
2351 register_file.fill(Definition(renamed.id(), var.reg, var.rc));
2571 if (affinity.assigned && affinity.reg != instr->operands[2].physReg() &&
2572 !register_file.test(affinity.reg, instr->operands[2].bytes()))
2626 if (affinity.assigned && affinity.reg != instr->operands[!literal_idx].physReg() &&
2627 !register_file.test(affinity.reg, instr->operands[!literal_idx].bytes()))
2731 phi_op.setFixed(ctx.assignments[phi_op.tempId()].reg);
2765 PhysReg reg = ctx.assignments[operand.tempId()].reg;
2766 if (operand_can_use_reg(program->gfx_level, instr, i, reg, operand.regClass()))
2767 operand.setFixed(reg);
2774 ctx.war_hint.set(operand.physReg().reg() + j);
2866 /* find free reg */
2868 PhysReg reg = instr->operands[0].physReg();
2871 reg.reg_b += instr->definitions[j].bytes();
2872 if (get_reg_specified(ctx, register_file, rc, instr, reg)) {
2873 definition->setFixed(reg);
2878 reg = res.first;
2879 if (res.second && get_reg_specified(ctx, register_file, rc, instr, reg))
2880 definition->setFixed(reg);
2882 reg = instr->definitions[i - 1].physReg();
2883 reg.reg_b += instr->definitions[i - 1].bytes();
2884 if (get_reg_specified(ctx, register_file, rc, instr, reg))
2885 definition->setFixed(reg);
2889 PhysReg reg = instr->operands[i].physReg();
2892 !register_file.test(reg, definition->bytes()))
2893 definition->setFixed(reg);
2895 PhysReg reg = instr->operands[0].physReg();
2896 reg.reg_b += definition->bytes() * instr->operands[1].constantValue();
2897 if (get_reg_specified(ctx, register_file, definition->regClass(), instr, reg))
2898 definition->setFixed(reg);
2900 PhysReg reg = get_reg_create_vector(ctx, register_file, definition->getTemp(),
2903 definition->setFixed(reg);
2909 PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, instr);
2910 definition->setFixed(reg);
2911 if (reg.byte() || register_file.test(reg, 4)) {
2912 add_subdword_definition(program, instr, reg);
2964 unsigned reg = parallelcopy[i].first.physReg().reg();
2966 sgpr_operands[reg / 64u] |= u_bit_consecutive64(reg % 64u, size);
2968 reg = parallelcopy[i].second.physReg().reg();
2970 if (sgpr_operands[reg / 64u] & u_bit_consecutive64(reg % 64u, size))
3027 /* if the first operand is a literal, we have to move it to a reg */
3048 PhysReg reg = get_reg(ctx, tmp_file, tmp, parallelcopy, instr);
3060 mov->definitions[0].setFixed(reg);
3063 instr->operands[0].setFixed(reg);