Lines Matching defs:instructions
66 * (2) The second pass combines instructions like mad, omod, clamp and
67 * propagates sgpr's on VALU instructions.
69 * (3) The third pass goes backwards, and selects instructions,
72 * instructions are removed from the sequence.
503 std::vector<aco_ptr<Instruction>> instructions;
545 /* don't propagate VGPRs into SGPR instructions */
574 * propagated by p_as_uniform instructions.
932 /* The accumulation operand of dot product instructions ignores opsel. */
1334 /* for instructions other than v_cndmask_b32, the size of the instruction should match the
2051 * neg/abs instructions because we'll likely combine it into another valu. */
2661 /* TODO: this can handle SDWA min/max instructions by using opsel */
3792 * label_extract if not all instructions can take SDWA. */
4262 /* Don't transform other instructions. They are very unlikely to appear here. */
4368 /* re-check mad instructions */
4388 * literals (GFX10+), these instructions don't exist.
4438 * because both instructions are 64-bit and this doesn't increase
4756 ctx.instructions.emplace_back(std::move(new_mad));
4784 ctx.instructions.emplace_back(std::move(instr));
4798 for (aco_ptr<Instruction>& instr : block.instructions)
4804 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
4807 for (aco_ptr<Instruction>& instr : block.instructions)
4811 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
4816 for (auto instr_rit = block->instructions.rbegin(); instr_rit != block->instructions.rend();
4821 /* 4. Add literals to instructions */
4823 ctx.instructions.clear();
4825 for (aco_ptr<Instruction>& instr : block.instructions)
4827 block.instructions.swap(ctx.instructions);