Lines Matching defs:instr
187 get_sync_info(const Instruction* instr)
189 switch (instr->format) {
190 case Format::SMEM: return instr->smem().sync;
191 case Format::MUBUF: return instr->mubuf().sync;
192 case Format::MIMG: return instr->mimg().sync;
193 case Format::MTBUF: return instr->mtbuf().sync;
196 case Format::SCRATCH: return instr->flatlike().sync;
197 case Format::DS: return instr->ds().sync;
203 can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra)
205 if (!instr->isVALU())
208 if (gfx_level < GFX8 || gfx_level >= GFX11 || instr->isDPP() || instr->isVOP3P())
211 if (instr->isSDWA())
214 if (instr->isVOP3()) {
215 VOP3_instruction& vop3 = instr->vop3();
216 if (instr->format == Format::VOP3)
218 if (vop3.clamp && instr->isVOPC() && gfx_level != GFX8)
224 if (!pre_ra && instr->definitions.size() >= 2)
227 for (unsigned i = 1; i < instr->operands.size(); i++) {
228 if (instr->operands[i].isLiteral())
230 if (gfx_level < GFX9 && !instr->operands[i].isOfType(RegType::vgpr))
235 if (!instr->definitions.empty() && instr->definitions[0].bytes() > 4 && !instr->isVOPC())
238 if (!instr->operands.empty()) {
239 if (instr->operands[0].isLiteral())
241 if (gfx_level < GFX9 && !instr->operands[0].isOfType(RegType::vgpr))
243 if (instr->operands[0].bytes() > 4)
245 if (instr->operands.size() > 1 && instr->operands[1].bytes() > 4)
249 bool is_mac = instr->opcode == aco_opcode::v_mac_f32 || instr->opcode == aco_opcode::v_mac_f16 ||
250 instr->opcode == aco_opcode::v_fmac_f32 || instr->opcode == aco_opcode::v_fmac_f16;
256 if (!pre_ra && instr->isVOPC() && gfx_level == GFX8)
258 if (!pre_ra && instr->operands.size() >= 3 && !is_mac)
261 return instr->opcode != aco_opcode::v_madmk_f32 && instr->opcode != aco_opcode::v_madak_f32 &&
262 instr->opcode != aco_opcode::v_madmk_f16 && instr->opcode != aco_opcode::v_madak_f16 &&
263 instr->opcode != aco_opcode::v_readfirstlane_b32 &&
264 instr->opcode != aco_opcode::v_clrexcp && instr->opcode != aco_opcode::v_swap_b32;
267 /* updates "instr" and returns the old instruction (or NULL if no update was needed) */
269 convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr)
271 if (instr->isSDWA())
274 aco_ptr<Instruction> tmp = std::move(instr);
277 instr.reset(create_instruction<SDWA_instruction>(tmp->opcode, format, tmp->operands.size(),
279 std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
280 std::copy(tmp->definitions.cbegin(), tmp->definitions.cend(), instr->definitions.begin());
282 SDWA_instruction& sdwa = instr->sdwa();
292 for (unsigned i = 0; i < instr->operands.size(); i++) {
297 sdwa.sel[i] = SubdwordSel(instr->operands[i].bytes(), 0, false);
300 sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false);
302 if (instr->definitions[0].getTemp().type() == RegType::sgpr && gfx_level == GFX8)
303 instr->definitions[0].setFixed(vcc);
304 if (instr->definitions.size() >= 2)
305 instr->definitions[1].setFixed(vcc);
306 if (instr->operands.size() >= 3)
307 instr->operands[2].setFixed(vcc);
309 instr->pass_flags = tmp->pass_flags;
315 can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8)
317 assert(instr->isVALU() && !instr->operands.empty());
319 if (instr->isDPP())
320 return instr->isDPP8() == dpp8;
322 if (instr->operands.size() && instr->operands[0].isLiteral())
325 if (instr->isSDWA())
328 if (!pre_ra && (instr->isVOPC() || instr->definitions.size() > 1) &&
329 instr->definitions.back().physReg() != vcc)
332 if (!pre_ra && instr->operands.size() >= 3 && instr->operands[2].physReg() != vcc)
335 if (instr->isVOP3()) {
336 const VOP3_instruction* vop3 = &instr->vop3();
341 if (instr->format == Format::VOP3)
343 if (instr->operands.size() > 1 && !instr->operands[1].isOfType(RegType::vgpr))
348 return instr->opcode != aco_opcode::v_madmk_f32 && instr->opcode != aco_opcode::v_madak_f32 &&
349 instr->opcode != aco_opcode::v_madmk_f16 && instr->opcode != aco_opcode::v_madak_f16 &&
350 instr->opcode != aco_opcode::v_readfirstlane_b32 &&
351 instr->opcode != aco_opcode::v_cvt_f64_i32 &&
352 instr->opcode != aco_opcode::v_cvt_f64_f32 && instr->opcode != aco_opcode::v_cvt_f64_u32;
356 convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8)
358 if (instr->isDPP())
361 aco_ptr<Instruction> tmp = std::move(instr);
365 instr.reset(create_instruction<DPP8_instruction>(tmp->opcode, format, tmp->operands.size(),
368 instr.reset(create_instruction<DPP16_instruction>(tmp->opcode, format, tmp->operands.size(),
370 std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
371 for (unsigned i = 0; i < instr->definitions.size(); i++)
372 instr->definitions[i] = tmp->definitions[i];
375 DPP8_instruction* dpp = &instr->dpp8();
379 DPP16_instruction* dpp = &instr->dpp16();
391 if (instr->isVOPC() || instr->definitions.size() > 1)
392 instr->definitions.back().setFixed(vcc);
394 if (instr->operands.size() >= 3)
395 instr->operands[2].setFixed(vcc);
397 instr->pass_flags = tmp->pass_flags;
563 needs_exec_mask(const Instruction* instr)
565 if (instr->isVALU()) {
566 return instr->opcode != aco_opcode::v_readlane_b32 &&
567 instr->opcode != aco_opcode::v_readlane_b32_e64 &&
568 instr->opcode != aco_opcode::v_writelane_b32 &&
569 instr->opcode != aco_opcode::v_writelane_b32_e64;
572 if (instr->isVMEM() || instr->isFlatLike())
575 if (instr->isSALU() || instr->isBranch() || instr->isSMEM() || instr->isBarrier())
576 return instr->reads_exec();
578 if (instr->isPseudo()) {
579 switch (instr->opcode) {
585 for (Definition def : instr->definitions) {
589 return instr->reads_exec();
596 case aco_opcode::p_init_scratch: return instr->reads_exec();
756 can_swap_operands(aco_ptr<Instruction>& instr, aco_opcode* new_op)
758 if (instr->isDPP())
761 if (instr->operands[0].isConstant() ||
762 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr))
765 switch (instr->opcode) {
792 case aco_opcode::v_min_u16_e64: *new_op = instr->opcode; return true;
800 if (get_cmp_info(instr->opcode, &info) && info.swapped != aco_opcode::num_opcodes) {