Lines Matching refs:idx
340 emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
343 bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand::c32(idx));
347 emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
351 assert(idx == 0);
355 assert(src.bytes() > (idx * dst_rc.bytes()));
358 if (it != ctx->allocated_vec.end() && dst_rc.bytes() == it->second[idx].regClass().bytes()) {
359 if (it->second[idx].regClass() == dst_rc) {
360 return it->second[idx];
363 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
364 return bld.copy(bld.def(dst_rc), it->second[idx]);
372 assert(idx == 0);
376 emit_extract_vector(ctx, src, idx, dst);
1417 unsigned idx = i * instr->dest.dest.ssa.bit_size / packed_size;
1420 const_vals[idx] |= nir_src_as_uint(instr->src[i].src) << offset;
1432 if (packed[idx].id())
1433 packed[idx] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), elems[i],
1434 packed[idx]);
1436 packed[idx] = elems[i];
4774 unsigned idx = 0;
4779 dst[i] = bld.as_uniform(temps[idx++]);
4781 dst[i] = as_vgpr(ctx, temps[idx++]);
4788 Temp tmp = temps[idx++];
5175 unsigned idx = nir_intrinsic_base(instr) * 4u + component;
5190 ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
5191 ctx->outputs.temps[idx] = emit_extract_vector(ctx, src, i, rc);
5193 idx++;
5231 unsigned idx = nir_intrinsic_base(instr) * 4u + nir_intrinsic_component(instr) +
5233 Temp* src = &ctx->inputs.temps[idx];
5259 emit_interp_instr(isel_context* ctx, unsigned idx, unsigned component, Temp src, Temp dst,
5272 bld.m0(prim_mask), idx, component);
5274 bld.m0(prim_mask), interp_p1, idx, component);
5276 interp_p1, idx, component);
5284 bld.m0(prim_mask), idx, component);
5285 bld.vintrp(interp_p2_op, Definition(dst), coord2, bld.m0(prim_mask), interp_p1, idx,
5290 bld.m0(prim_mask), idx, component);
5296 idx, component);
5360 unsigned idx = nir_intrinsic_base(instr);
5367 emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
5373 emit_interp_instr(ctx, idx, component + i, coords, tmp, prim_mask);
5670 unsigned idx = i + component;
5671 if (idx < num_channels && channels[idx].id()) {
5672 Temp channel = channels[idx];
5677 } else if (is_float && idx == 3) {
5679 } else if (!is_float && idx == 3) {
5699 unsigned idx = nir_intrinsic_base(instr);
5722 bld.m0(prim_mask), idx, component);
5731 unsigned chan_idx = idx + (component + i) / 4;
10323 unsigned idx = ctx->block->index;
10327 add_logical_edge(idx, logical_target);
10336 add_linear_edge(idx, logical_target);
10342 add_logical_edge(idx, logical_target);
10350 add_linear_edge(idx, logical_target);
10369 add_linear_edge(idx, break_block);
10378 add_linear_edge(idx, continue_block);
10440 for (unsigned idx = first + 1; idx <= last; idx++) {
10441 Block& block = ctx->program->blocks[idx];
10443 vals[idx - first] = vals[idx - 1 - first];
10448 vals[idx - first] = header_phi->operands[next_pred];
10469 vals[idx - first] = val;
11628 unsigned idx = ctx->args->vs_inputs[i].arg_index;
11629 def.setFixed(PhysReg(256 + ctx->args->ac.args[idx].offset));
11794 for (unsigned idx : BB.linear_preds)
11795 program->blocks[idx].linear_succs.emplace_back(BB.index);
11796 for (unsigned idx : BB.logical_preds)
11797 program->blocks[idx].logical_succs.emplace_back(BB.index);