Lines Matching defs:mask
136 emit_mbcnt(isel_context* ctx, Temp dst, Operand mask = Operand(), Operand base = Operand::zero())
139 assert(mask.isUndefined() || mask.isTemp() || (mask.isFixed() && mask.physReg() == exec));
140 assert(mask.isUndefined() || mask.bytes() == bld.lm.bytes());
143 Operand mask_lo = mask.isUndefined() ? Operand::c32(-1u) : mask;
150 if (mask.isTemp()) {
151 RegClass rc = RegClass(mask.regClass().type(), 1);
153 bld.pseudo(aco_opcode::p_split_vector, bld.def(rc), bld.def(rc), mask);
156 } else if (mask.physReg() == exec) {
234 emit_masked_swizzle(isel_context* ctx, Builder& bld, Temp src, unsigned mask)
237 unsigned and_mask = mask & 0x1f;
238 unsigned or_mask = (mask >> 5) & 0x1f;
239 unsigned xor_mask = (mask >> 10) & 0x1f;
268 return bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false);
412 /* This vector expansion uses a mask to determine which elements in the new vector
415 expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask,
423 expand_vector(ctx, vec_src, tmp_dst, num_components, mask, zero_padding);
429 emit_split_vector(ctx, vec_src, util_bitcount(mask));
457 if (mask & (1 << i)) {
571 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
1313 Temp mask = bld.copy(bld.def(s1), Operand::c32(3u)); /* isnan */
1317 Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.def(bld.lm), src0, mask);
1411 Temp mask = bld.copy(bld.def(s1), Operand::c32((1u << instr->dest.dest.ssa.bit_size) - 1));
1426 bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), elems[i], mask);
3601 Temp mask = bld.copy(
3603 cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.def(bld.lm), f16, mask);
3698 Temp mask = bld.sop2(aco_opcode::s_bfm_b32, bld.def(s1), bits, offset);
3700 bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), base, mask);
4800 scan_write_mask(uint32_t mask, uint32_t todo_mask, int* start, int* count)
4803 bool skip = !(mask & (1 << start_elem));
4805 mask = ~mask & todo_mask;
4807 mask &= todo_mask;
4809 u_bit_scan_consecutive_range(&mask, start, count);
5190 ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
5506 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
5507 unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
5543 channel_start = ffs(mask) - 1;
5845 uint64_t mask = BITFIELD64_MASK(count) << start;
5846 if ((ctx->args->ac.inline_push_const_mask | mask) == ctx->args->ac.inline_push_const_mask &&
7753 if (ctx->outputs.mask[i] & (1 << j)) {
7784 ctx->outputs.mask[i] = 0;
8933 uint32_t mask = nir_intrinsic_swizzle_mask(instr);
8942 src = emit_masked_swizzle(ctx, bld, src, mask);
8946 Temp tmp = emit_wqm(bld, emit_masked_swizzle(ctx, bld, src, mask));
8949 Temp tmp = emit_wqm(bld, emit_masked_swizzle(ctx, bld, src, mask));
8952 emit_wqm(bld, emit_masked_swizzle(ctx, bld, src, mask), dst);
8956 lo = emit_wqm(bld, emit_masked_swizzle(ctx, bld, lo, mask));
8957 hi = emit_wqm(bld, emit_masked_swizzle(ctx, bld, hi, mask));
8991 /* Fit 64-bit mask for wave32 */
10064 unsigned mask = instr->op == nir_texop_tg4 ? (instr->is_sparse ? 0x1F : 0xF) : dmask;
10065 expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
10242 /* Discards can result in code running with an empty exec mask.
10244 * workaround, break the loop when the loop mask is empty instead of
10692 /* uniform control flow never has an empty exec-mask */
10898 unsigned mask = ctx->outputs.mask[slot];
10899 if (!is_pos && !mask)
10905 exp->enabled_mask = mask;
10907 if (mask & (1 << i))
10934 if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
10938 if (ctx->outputs.mask[VARYING_SLOT_LAYER] && !outinfo->writes_layer_per_primitive) {
10942 if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT] && !outinfo->writes_viewport_index_per_primitive) {
10958 if (ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_SHADING_RATE]) {
10986 ctx->outputs.mask[VARYING_SLOT_POS] = 0xf;
11060 en_mask /* enabled mask */, V_008DFC_SQ_EXP_PRIM /* dest */, false /* compressed */,
11061 true /* done */, false /* valid mask */);
11086 /* Both stencil and sample mask only need 16-bits. */
11105 (ctx->outputs.mask[FRAG_RESULT_DATA0] & 0x8)) {
11112 /* Ignore the high 16 bits of the sample mask. */
11137 (ctx->outputs.mask[FRAG_RESULT_DATA0] & 0x8)) {
11333 /* GFX11 doesn't use COMPR for exports, but the channel mask should be
11369 unsigned write_mask = ctx->outputs.mask[slot];
11415 /* Export depth, stencil and sample mask. */
11416 if (ctx->outputs.mask[FRAG_RESULT_DEPTH] || ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
11417 ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK])
11425 if (!ctx->outputs.mask[i])
11431 out.write_mask = ctx->outputs.mask[i];
11461 unsigned writemask = output->component_mask & ctx->outputs.mask[loc];
11807 Temp mask = bld.sop2(aco_opcode::s_bfm_b64, bld.def(s2), count, Operand::zero());
11811 /* If we know that all 64 threads can't be active at a time, we just use the mask as-is */
11813 return mask;
11819 bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand::c32(-1u), mask, bld.scc(active_64));
11823 cond = emit_extract_vector(ctx, mask, 0, bld.lm);
11894 bld.exp(aco_opcode::exp, zero, Operand(v1), Operand(v1), Operand(v1), 1 /* enabled mask */,
11896 false /* valid mask */);
11897 bld.exp(aco_opcode::exp, nan_coord, nan_coord, nan_coord, nan_coord, 0xf /* enabled mask */,
11899 true /* valid mask */);
12074 memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
12100 ctx.outputs.mask[i] |= 1 << j;