Lines Matching refs:physReg
220 if (regs_intersect(reg, mask_size, def.physReg(), def.size())) {
221 unsigned start = def.physReg() > reg ? def.physReg() - reg : 0;
282 state, state.block, min_states, op.physReg(), u_bit_consecutive(0, op.size()), false);
343 test_bitset_range(ctx.smem_clause_write, op.physReg(), op.size())) {
350 if (!*NOPs && test_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size()))
406 if (op.physReg() == vccz)
408 if (op.physReg() == execz)
420 NOPs = MAX2(NOPs, ctx.vmem_store_then_wr_data[(def.physReg() & 0xff) + i]);
499 set_bitset_range(ctx.smem_clause_read_write, op.physReg(), op.size());
504 set_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size());
505 set_bitset_range(ctx.smem_clause_write, def.physReg(), def.size());
511 if (def.physReg() == vcc || def.physReg() == vcc_hi) {
515 if (def.physReg() == exec || def.physReg() == exec_hi) {
525 if (def.physReg() == m0) {
544 instr->operands[3].size() > 2 && instr->operands[2].physReg() >= 128;
554 PhysReg wrdata = instr->operands[consider_flat ? 2 : 3].physReg();
571 unsigned def_reg = def.physReg() + i;
584 unsigned reg = op.physReg() + i;
620 { return def.physReg() == exec_lo || def.physReg() == exec_hi; });
714 v_mov->definitions[0] = Definition(instr->operands[0].physReg(), v1);
715 v_mov->operands[0] = Operand(instr->operands[0].physReg(), v1);
772 if (sopp.imm == 0 && sopp.definitions[0].physReg() == sgpr_null)
801 if (sopk.definitions[0].physReg() == sgpr_null && sopk.imm == 0)