Lines Matching refs:instr
50 // and, when emitting the block, correct the offset in instr
65 get_mimg_nsa_dwords(const Instruction* instr)
67 unsigned addr_dwords = instr->operands.size() - 3;
69 if (instr->operands[3 + i].physReg() != instr->operands[3].physReg().advance(i * 4))
76 emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* instr)
79 if (instr->opcode == aco_opcode::p_constaddr_getpc) {
80 ctx.constaddrs[instr->operands[0].constantValue()].getpc_end = out.size() + 1;
82 instr->opcode = aco_opcode::s_getpc_b64;
83 instr->operands.pop_back();
84 } else if (instr->opcode == aco_opcode::p_constaddr_addlo) {
85 ctx.constaddrs[instr->operands[2].constantValue()].add_literal = out.size() + 1;
87 instr->opcode = aco_opcode::s_add_u32;
88 instr->operands.pop_back();
89 assert(instr->operands[1].isConstant());
91 instr->operands[1] = Operand::literal32(instr->operands[1].constantValue());
94 uint32_t opcode = ctx.opcode[(int)instr->opcode];
103 aco_print_instr(instr, memf);
112 switch (instr->format) {
116 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0;
117 encoding |= instr->operands.size() >= 2 ? instr->operands[1].physReg() << 8 : 0;
118 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
123 SOPK_instruction& sopk = instr->sopk();
125 if (instr->opcode == aco_opcode::s_subvector_loop_begin) {
129 } else if (instr->opcode == aco_opcode::s_subvector_loop_end) {
141 encoding |= !instr->definitions.empty() && !(instr->definitions[0].physReg() == scc)
142 ? instr->definitions[0].physReg() << 16
143 : !instr->operands.empty() && instr->operands[0].physReg() <= 127
144 ? instr->operands[0].physReg() << 16
152 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0;
154 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
161 encoding |= instr->operands.size() == 2 ? instr->operands[1].physReg() << 8 : 0;
162 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
167 SOPP_instruction& sopp = instr->sopp();
179 SMEM_instruction& smem = instr->smem();
180 bool soe = instr->operands.size() >= (!instr->definitions.empty() ? 3 : 4);
181 bool is_load = !instr->definitions.empty();
187 encoding |= instr->definitions.size() ? instr->definitions[0].physReg() << 15 : 0;
188 encoding |= instr->operands.size() ? (instr->operands[0].physReg() >> 1) << 9 : 0;
189 if (instr->operands.size() >= 2) {
190 if (!instr->operands[1].isConstant()) {
191 encoding |= instr->operands[1].physReg().reg();
192 } else if (instr->operands[1].constantValue() >= 1024) {
195 encoding |= instr->operands[1].constantValue() >> 2;
201 if (instr->operands.size() >= 2 && instr->operands[1].isConstant() &&
202 instr->operands[1].constantValue() >= 1024)
203 out.push_back(instr->operands[1].constantValue() >> 2);
221 if (instr->operands.size() >= 2)
222 encoding |= instr->operands[1].isConstant() ? 1 << 17 : 0; /* IMM - immediate enable */
228 if (is_load || instr->operands.size() >= 3) { /* SDATA */
229 encoding |= (is_load ? instr->definitions[0].physReg() : instr->operands[2].physReg())
232 if (instr->operands.size() >= 1) { /* SBASE */
233 encoding |= instr->operands[0].physReg() >> 1;
244 if (instr->operands.size() >= 2) {
245 const Operand& op_off1 = instr->operands[1];
260 const Operand& op_off2 = instr->operands.back();
276 encoding |= (0xFF & instr->definitions[0].physReg()) << 17;
277 encoding |= (0xFF & instr->operands[1].physReg()) << 9;
278 encoding |= instr->operands[0].physReg();
284 if (!instr->definitions.empty())
285 encoding |= (0xFF & instr->definitions[0].physReg()) << 17;
287 if (!instr->operands.empty())
288 encoding |= instr->operands[0].physReg();
295 encoding |= (0xFF & instr->operands[1].physReg()) << 9;
296 encoding |= instr->operands[0].physReg();
301 Interp_instruction& interp = instr->vintrp();
304 if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
305 instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
306 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
307 instr->opcode == aco_opcode::v_interp_p2_f16) {
317 encoding |= (0xFF & instr->definitions[0].physReg());
323 encoding |= instr->operands[0].physReg() << 9;
324 if (instr->opcode == aco_opcode::v_interp_p2_f16 ||
325 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
326 instr->opcode == aco_opcode::v_interp_p1lv_f16) {
327 encoding |= instr->operands[2].physReg() << 18;
338 encoding |= (0xFF & instr->definitions[0].physReg()) << 18;
342 if (instr->opcode == aco_opcode::v_interp_mov_f32)
343 encoding |= (0x3 & instr->operands[0].constantValue());
345 encoding |= (0xFF & instr->operands[0].physReg());
351 DS_instruction& ds = instr->ds();
364 unsigned reg = !instr->definitions.empty() ? instr->definitions[0].physReg() : 0;
366 reg = instr->operands.size() >= 3 && !(instr->operands[2].physReg() == m0)
367 ? instr->operands[2].physReg()
370 reg = instr->operands.size() >= 2 && !(instr->operands[1].physReg() == m0)
371 ? instr->operands[1].physReg()
374 encoding |= (0xFF & instr->operands[0].physReg());
379 MUBUF_instruction& mubuf = instr->mubuf();
401 encoding |= instr->operands[2].physReg() << 24;
403 encoding |= (instr->operands[0].physReg() >> 2) << 16;
404 unsigned reg = instr->operands.size() > 3 ? instr->operands[3].physReg()
405 : instr->definitions[0].physReg();
407 encoding |= (0xFF & instr->operands[1].physReg());
412 MTBUF_instruction& mtbuf = instr->mtbuf();
434 encoding |= instr->operands[2].physReg() << 24;
437 encoding |= (instr->operands[0].physReg() >> 2) << 16;
438 unsigned reg = instr->operands.size() > 3 ? instr->operands[3].physReg()
439 : instr->definitions[0].physReg();
441 encoding |= (0xFF & instr->operands[1].physReg());
451 unsigned nsa_dwords = get_mimg_nsa_dwords(instr);
454 MIMG_instruction& mimg = instr->mimg();
477 encoding = (0xFF & instr->operands[3].physReg()); /* VADDR */
478 if (!instr->definitions.empty()) {
479 encoding |= (0xFF & instr->definitions[0].physReg()) << 8; /* VDATA */
480 } else if (!instr->operands[2].isUndefined()) {
481 encoding |= (0xFF & instr->operands[2].physReg()) << 8; /* VDATA */
483 encoding |= (0x1F & (instr->operands[0].physReg() >> 2)) << 16; /* T# (resource) */
484 if (!instr->operands[1].isUndefined())
485 encoding |= (0x1F & (instr->operands[1].physReg() >> 2)) << 21; /* sampler */
499 for (unsigned i = 0; i < instr->operands.size() - 4u; i++)
500 nsa[i / 4] |= (0xFF & instr->operands[4 + i].physReg().reg()) << (i % 4 * 8);
507 FLAT_instruction& flat = instr->flatlike();
511 if (instr->isFlat())
516 } else if (ctx.gfx_level <= GFX8 || instr->isFlat()) {
525 if (instr->isScratch())
527 else if (instr->isGlobal())
539 encoding = (0xFF & instr->operands[0].physReg());
540 if (!instr->definitions.empty())
541 encoding |= (0xFF & instr->definitions[0].physReg()) << 24;
542 if (instr->operands.size() >= 3)
543 encoding |= (0xFF & instr->operands[2].physReg()) << 8;
544 if (!instr->operands[1].isUndefined()) {
545 assert(ctx.gfx_level >= GFX10 || instr->operands[1].physReg() != 0x7F);
546 assert(instr->format != Format::FLAT);
547 encoding |= instr->operands[1].physReg() << 16;
548 } else if (instr->format != Format::FLAT ||
554 (instr->format == Format::SCRATCH && instr->operands[0].isUndefined()))
564 Export_instruction& exp = instr->exp();
587 if (instr->opcode != aco_opcode::p_unit_test)
591 if (instr->isVOP3()) {
592 VOP3_instruction& vop3 = instr->vop3();
594 if (instr->isVOP2()) {
596 } else if (instr->isVOP1()) {
601 } else if (instr->isVOPC()) {
603 } else if (instr->isVINTRP()) {
626 if (instr->definitions.size() == 2)
627 encoding |= instr->definitions[1].physReg() << 8;
628 encoding |= (0xFF & instr->definitions[0].physReg());
631 if (instr->opcode == aco_opcode::v_interp_mov_f32) {
632 encoding = 0x3 & instr->operands[0].constantValue();
633 } else if (instr->opcode == aco_opcode::v_writelane_b32_e64) {
634 encoding |= instr->operands[0].physReg() << 0;
635 encoding |= instr->operands[1].physReg() << 9;
638 for (unsigned i = 0; i < instr->operands.size(); i++)
639 encoding |= instr->operands[i].physReg() << (i * 9);
646 } else if (instr->isVOP3P()) {
647 VOP3P_instruction& vop3 = instr->vop3p();
664 encoding |= (0xFF & instr->definitions[0].physReg());
667 for (unsigned i = 0; i < instr->operands.size(); i++)
668 encoding |= instr->operands[i].physReg() << (i * 9);
674 } else if (instr->isDPP16()) {
676 DPP16_instruction& dpp = instr->dpp16();
679 Operand dpp_op = instr->operands[0];
680 instr->operands[0] = Operand(PhysReg{250}, v1);
681 instr->format = (Format)((uint16_t)instr->format & ~(uint16_t)Format::DPP16);
682 emit_instruction(ctx, out, instr);
696 } else if (instr->isDPP8()) {
698 DPP8_instruction& dpp = instr->dpp8();
701 Operand dpp_op = instr->operands[0];
702 instr->operands[0] = Operand(PhysReg{234}, v1);
703 instr->format = (Format)((uint16_t)instr->format & ~(uint16_t)Format::DPP8);
704 emit_instruction(ctx, out, instr);
710 } else if (instr->isSDWA()) {
712 SDWA_instruction& sdwa = instr->sdwa();
715 Operand sdwa_op = instr->operands[0];
716 instr->operands[0] = Operand(PhysReg{249}, v1);
717 instr->format = (Format)((uint16_t)instr->format & ~(uint16_t)Format::SDWA);
718 emit_instruction(ctx, out, instr);
722 if (instr->isVOPC()) {
723 if (instr->definitions[0].physReg() != vcc) {
724 encoding |= instr->definitions[0].physReg() << 8;
729 encoding |= sdwa.dst_sel.to_sdwa_sel(instr->definitions[0].physReg().byte()) << 8;
731 if (instr->definitions[0].bytes() < 4) /* dst_preserve */
743 if (instr->operands.size() >= 2) {
744 encoding |= sdwa.sel[1].to_sdwa_sel(instr->operands[1].physReg().byte()) << 24;
752 if (instr->operands.size() >= 2)
753 encoding |= (instr->operands[1].physReg() < 256) << 31;
762 for (const Operand& op : instr->operands) {
773 for (aco_ptr<Instruction>& instr : block.instructions) {
777 aco_print_instr(&*instr, stderr);
780 emit_instruction(ctx, out, instr.get());
904 aco_ptr<Instruction> instr;
918 instr.reset(bld.sopp(inv, -1, 6));
919 emit_instruction(ctx, out, instr.get());
923 instr.reset(bld.sop1(aco_opcode::s_getpc_b64, branch->definitions[0]).instr);
924 emit_instruction(ctx, out, instr.get());
926 instr.reset(
927 bld.sop2(aco_opcode::s_addc_u32, def_tmp_lo, op_tmp_lo, Operand::literal32(0)).instr);
928 emit_instruction(ctx, out, instr.get());
934 instr.reset(bld.sopc(aco_opcode::s_bitcmp1_b32, def_tmp_lo, op_tmp_lo, Operand::zero()).instr);
935 emit_instruction(ctx, out, instr.get());
936 instr.reset(bld.sop1(aco_opcode::s_bitset0_b32, def_tmp_lo, Operand::zero()).instr);
937 emit_instruction(ctx, out, instr.get());
940 instr.reset(
941 bld.sop1(aco_opcode::s_setpc_b64, Operand(branch->definitions[0].physReg(), s2)).instr);
942 emit_instruction(ctx, out, instr.get());