Lines Matching refs:info
191 bool ac_is_modifier_supported(const struct radeon_info *info,
202 if (info->gfx_level < GFX9)
209 if (info->gfx_level < GFX9 && util_format_get_num_planes(format) > 1)
213 switch(info->gfx_level) {
236 if (!info->has_graphics)
249 bool ac_get_supported_modifiers(const struct radeon_info *info,
258 if (ac_is_modifier_supported(info, options, format, (name))) { \
267 switch (info->gfx_level) {
269 unsigned pipe_xor_bits = MIN2(G_0098F8_NUM_PIPES(info->gb_addr_config) +
270 G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config), 8);
271 unsigned bank_xor_bits = MIN2(G_0098F8_NUM_BANKS(info->gb_addr_config), 8 - pipe_xor_bits);
272 unsigned pipes = G_0098F8_NUM_PIPES(info->gb_addr_config);
273 unsigned rb = G_0098F8_NUM_RB_PER_SE(info->gb_addr_config) +
274 G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config);
279 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, info->has_dcc_constant_encode) |
300 if (info->max_render_backends == 1) {
343 bool rbplus = info->gfx_level >= GFX10_3;
344 unsigned pipe_xor_bits = G_0098F8_NUM_PIPES(info->gb_addr_config);
345 unsigned pkrs = rbplus ? G_0098F8_NUM_PKRS(info->gb_addr_config) : 0;
360 if (info->gfx_level >= GFX10_3) {
399 unsigned pipe_xor_bits = G_0098F8_NUM_PIPES(info->gb_addr_config);
400 unsigned pkrs = G_0098F8_NUM_PKRS(info->gb_addr_config);
414 if (!info->has_dedicated_vram && swizzle_r_x == AMD_FMT_MOD_TILE_GFX11_256K_R_X)
495 struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info,
508 regValue.gbAddrConfig = info->gb_addr_config;
511 addrCreateInput.chipFamily = info->family_id;
512 addrCreateInput.chipRevision = info->chip_external_rev;
520 regValue.noOfBanks = info->mc_arb_ramcfg & 0x3;
521 regValue.noOfRanks = (info->mc_arb_ramcfg & 0x4) >> 2;
523 regValue.backendDisables = info->enabled_rb_mask;
524 regValue.pTileConfig = info->si_tile_mode_array;
525 regValue.noOfEntries = ARRAY_SIZE(info->si_tile_mode_array);
530 regValue.pMacroTileConfig = info->cik_macrotile_mode_array;
531 regValue.noOfMacroEntries = ARRAY_SIZE(info->cik_macrotile_mode_array);
590 if (!config->info.width || !config->info.height || !config->info.depth ||
591 !config->info.array_size || !config->info.levels)
594 switch (config->info.samples) {
610 switch (config->info.storage_samples) {
622 if (config->is_3d && config->info.array_size > 1)
624 if (config->is_cube && config->info.depth > 1)
644 AddrSurfInfoIn->width = u_minify(config->info.width, level);
645 AddrSurfInfoIn->height = u_minify(config->info.height, level);
650 if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
660 assert(config->info.levels == 1);
669 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
673 AddrSurfInfoIn->numSlices = config->info.array_size;
770 (prev_level_clearable && level == config->info.levels - 1))
776 * provide this info. As DCC memory is linear (each
779 surf->meta_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
781 /* For arrays, we have to compute the DCC info again
785 if (config->info.array_size > 1) {
843 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, const struct radeon_info *info)
845 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
847 if (info->gfx_level >= GFX7)
869 unsigned num_channels = config->info.num_channels;
881 surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 &&
904 static int gfx6_surface_settings(ADDR_HANDLE addrlib, const struct radeon_info *info,
910 gfx6_set_micro_tile_mode(surf, info);
926 if ((info->gfx_level >= GFX7 || config->info.levels == 1) && config->info.surf_index &&
936 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
953 static void ac_compute_cmask(const struct radeon_info *info, const struct ac_surf_config *config,
956 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
957 unsigned num_pipes = info->num_tile_pipes;
961 (config->info.samples >= 2 && !surf->fmask_size))
964 assert(info->gfx_level <= GFX8);
1003 num_layers = config->info.depth;
1007 num_layers = config->info.array_size;
1020 static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1047 if (config->info.samples > 1)
1093 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1097 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1112 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
1120 !AddrSurfInfoIn.flags.fmask && config->info.samples <= 1 &&
1130 info->gfx_level >= GFX8 && info->has_graphics && /* disable DCC on compute-only chips */
1133 ((config->info.array_size == 1 && config->info.depth == 1) || config->info.levels == 1);
1158 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
1195 if (info->gfx_level == GFX6) {
1235 for (level = 0; level < config->info.levels; level++) {
1258 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1274 for (level = 0; level < config->info.levels; level++) {
1290 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1304 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color && info->has_graphics &&
1315 fin.height = config->info.height;
1340 if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) {
1348 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1367 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_size && config->info.levels > 1) {
1383 surf->meta_size && config->info.levels > 1) {
1410 ac_compute_cmask(info, config, surf);
1415 static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct radeon_info *info,
1435 if (info->gfx_level >= GFX11) {
1437 if (!info->has_dedicated_vram) {
1465 if (info->gfx_level >= GFX11) {
1485 if (info->gfx_level >= GFX10 && in->resourceType == ADDR_RSRC_TEX_3D && in->numSlices > 1) {
1510 static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
1512 if (info->gfx_level >= GFX11)
1516 if (info->gfx_level >= GFX10)
1522 ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info,
1525 if (info->gfx_level <= GFX9) {
1531 if (info->family == CHIP_NAVI10) {
1542 if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14) {
1557 static bool gfx10_DCN_requires_independent_64B_blocks(const struct radeon_info *info,
1560 assert(info->gfx_level >= GFX10);
1563 if (info->drm_minor <= 43)
1567 return config->info.width > 2560 || config->info.height > 2560;
1570 void ac_modifier_max_extent(const struct radeon_info *info,
1582 if (info->gfx_level >= GFX10 && !independent_64B_blocks) {
1590 static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
1595 if (!info->use_display_dcc_unaligned && !info->use_display_dcc_with_retile_blit)
1603 if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned))
1606 switch (info->gfx_level) {
1624 if (info->gfx_level == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
1627 return (!gfx10_DCN_requires_independent_64B_blocks(info, config) ||
1636 static void ac_copy_dcc_equation(const struct radeon_info *info,
1644 if (info->gfx_level >= GFX10) {
1668 static void ac_copy_cmask_equation(const struct radeon_info *info,
1676 if (info->gfx_level == GFX9) {
1690 static void ac_copy_htile_equation(const struct radeon_info *info,
1708 static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_info *info,
1733 if (info->gfx_level >= GFX10)
1850 if (info->gfx_level >= GFX10)
1851 ac_copy_htile_equation(info, &hout, &surf->u.gfx9.zs.htile_equation);
1859 if (config->info.surf_index && in->swizzleMode >= ADDR_SW_64KB_Z_T && !out.mipChainInTail &&
1867 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1887 use_dcc = info->has_graphics && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed &&
1888 is_dcc_supported_by_CB(info, in->swizzleMode) &&
1890 is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned,
1917 if (info->gfx_level == GFX9)
1920 if (info->gfx_level == GFX9)
1971 if (info->gfx_level >= GFX10)
1988 ac_copy_dcc_equation(info, &dout, &surf->u.gfx9.color.dcc_equation);
1991 if (((in->flags.display && info->use_display_dcc_with_retile_blit) ||
1993 /* Compute displayable DCC info. */
2003 if (info->gfx_level == GFX9)
2006 if (info->gfx_level == GFX9)
2018 ac_copy_dcc_equation(info, &dout, &surf->u.gfx9.color.display_dcc_equation);
2024 if (info->gfx_level <= GFX10_3 && info->has_graphics &&
2032 ret = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, in, true, &fin.swizzleMode);
2053 if (config->info.fmask_surf_index && fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
2062 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
2080 if (info->gfx_level <= GFX10_3 && info->has_graphics &&
2082 ((info->gfx_level <= GFX9 && in->numSamples == 1 && in->flags.metaPipeUnaligned == 0 &&
2110 if (info->gfx_level == GFX9)
2113 if (info->gfx_level == GFX9)
2127 ac_copy_cmask_equation(info, &cout, &surf->u.gfx9.color.cmask_equation);
2134 static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info,
2200 AddrSurfInfoIn.numMipLevels = config->info.levels;
2201 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
2205 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
2212 else if (info->gfx_level != GFX9 && config->is_1d)
2217 AddrSurfInfoIn.width = config->info.width;
2218 AddrSurfInfoIn.height = config->info.height;
2221 AddrSurfInfoIn.numSlices = config->info.depth;
2225 AddrSurfInfoIn.numSlices = config->info.array_size;
2237 if (info->gfx_level == GFX9) {
2241 } else if (info->gfx_level >= GFX10) {
2256 if (info->use_display_dcc_unaligned) {
2264 (info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit)) {
2268 if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14) {
2274 if ((info->gfx_level >= GFX10_3 && info->family <= CHIP_REMBRANDT) ||
2279 (info->family > CHIP_REMBRANDT &&
2280 gfx10_DCN_requires_independent_64B_blocks(info, config))) {
2292 assert(config->info.samples <= 1);
2300 (info->gfx_level >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) {
2305 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2342 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2354 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2361 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2380 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2383 (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.color.dcc.display_equation_valid)))
2393 assert(is_dcc_supported_by_L2(info, surf));
2395 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode));
2397 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2402 if (info->has_graphics && !compressed && !config->is_3d && config->info.levels == 1 &&
2408 is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2411 if ((info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit) &&
2466 assert(info->gfx_level >= GFX10 || !"rotate micro tile mode is unsupported");
2487 int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info,
2497 if (info->family_id >= FAMILY_AI)
2498 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
2500 r = gfx6_compute_surface(addrlib->handle, info, config, mode, surf);
2513 assert(config->info.samples >= 2);
2520 if (surf->cmask_size && config->info.samples >= 2) {
2531 (info->gfx_level >= GFX9 || !get_display_flag(config, surf))) {
2535 if (info->gfx_level >= GFX9 &&
2619 void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2624 if (info->gfx_level >= GFX9) {
2659 void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2664 if (info->gfx_level >= GFX9) {
2706 static uint32_t ac_get_umd_metadata_word1(const struct radeon_info *info)
2708 return (ATI_VENDOR_ID << 16) | info->pci_id;
2712 bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2722 if (info->gfx_level >= GFX9)
2730 metadata[1] != ac_get_umd_metadata_word1(info)) /* invalid PCI ID */ {
2764 if (info->gfx_level >= GFX8 && G_008F28_COMPRESSION_EN(desc[6])) {
2766 switch (info->gfx_level) {
2804 void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2812 switch (info->gfx_level) {
2848 metadata[1] = ac_get_umd_metadata_word1(info);
2855 if (info->gfx_level <= GFX8) {
2889 bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
2900 info->gfx_level >= GFX10;
2902 if (info->gfx_level >= GFX9) {
3027 void ac_surface_print_info(FILE *out, const struct radeon_info *info,
3030 if (info->gfx_level >= GFX9) {
3123 static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
3134 assert(info->gfx_level >= GFX10);
3161 unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) - 1;
3162 unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
3179 static nir_ssa_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
3189 assert(info->gfx_level >= GFX9);
3195 unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
3247 nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
3254 if (info->gfx_level >= GFX10) {
3257 return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1,
3261 return gfx9_nir_meta_addr_from_coord(b, info, equation, dcc_pitch,
3267 nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
3277 if (info->gfx_level >= GFX10) {
3278 return gfx10_nir_meta_addr_from_coord(b, info, equation, -7, 1,
3282 return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch,
3288 nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
3295 return gfx10_nir_meta_addr_from_coord(b, info, equation, -4, 2,