Lines Matching defs:level
439 * Top level order:
631 struct radeon_surf *surf, bool is_stencil, unsigned level,
643 AddrSurfInfoIn->mipLevel = level;
644 AddrSurfInfoIn->width = u_minify(config->info.width, level);
645 AddrSurfInfoIn->height = u_minify(config->info.height, level);
669 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
675 if (level > 0) {
676 /* Set the base level pitch. This is needed for calculation
681 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
693 surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level];
694 dcc_level = &surf->u.legacy.color.dcc_level[level];
717 surf->u.legacy.zs.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
719 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
722 if (level == 0) {
729 /* +1 because the current level is not in the miptail */
730 surf->first_mip_tail_level = level + 1;
740 /* The previous level's flag tells us if we can use DCC for this level. */
741 if (AddrSurfInfoIn->flags.dccCompatible && (level == 0 || AddrDccOut->subLvlCompressible)) {
742 bool prev_level_clearable = level == 0 || AddrDccOut->dccRamSizeAligned;
754 surf->num_meta_levels = level + 1;
758 /* If the DCC size of a subresource (1 mip level or 1 slice)
766 * The last level can be non-contiguous and still be clearable
767 * if it's interleaved with the next level that doesn't exist.
770 (prev_level_clearable && level == config->info.levels - 1))
818 level == 0 && !(surf->flags & RADEON_SURF_NO_HTILE)) {
836 surf->num_meta_levels = level + 1;
899 * This must be called after the first level is computed.
901 * Copy surface-global settings like pipe/bank config from level 0 surface
927 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
990 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
991 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
1024 unsigned level;
1235 for (level = 0; level < config->info.levels; level++) {
1236 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn,
1242 if (level > 0)
1274 for (level = 0; level < config->info.levels; level++) {
1275 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn,
1282 if (surf->u.legacy.zs.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
1285 surf->u.legacy.level[level].nblk_x = surf->u.legacy.zs.stencil_level[level].nblk_x;
1288 if (level == 0) {
1369 * still read the DCC buffer via TC if the base level uses DCC,
1396 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
1839 /* GFX10 can only compress the first level
1965 /* GFX10 can only compress the first level
2683 if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D)
2685 else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D)
2725 offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256;
2842 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
2854 /* Dwords [10:..] contain the mipmap level offsets. */
2857 metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
2924 if (surf->u.legacy.level[0].nblk_x != pitch && require_equal_pitch)
2927 surf->u.legacy.level[0].nblk_x = pitch;
2928 surf->u.legacy.level[0].slice_size_dw =
2929 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
2933 for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
2934 surf->u.legacy.level[i].offset_256B += offset / 256;
2975 return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 +
2976 layer * (uint64_t)surf->u.legacy.level[0].slice_size_dw * 4;
2992 unsigned plane, unsigned level)
2997 return (surf->is_linear ? surf->u.gfx9.pitch[level] : surf->u.gfx9.surf_pitch) * surf->bpe;
2999 return surf->u.legacy.level[level].nblk_x * surf->bpe;