Lines Matching defs:config
580 static int surf_config_sanity(const struct ac_surf_config *config, unsigned flags)
590 if (!config->info.width || !config->info.height || !config->info.depth ||
591 !config->info.array_size || !config->info.levels)
594 switch (config->info.samples) {
610 switch (config->info.storage_samples) {
622 if (config->is_3d && config->info.array_size > 1)
624 if (config->is_cube && config->info.depth > 1)
630 static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *config,
644 AddrSurfInfoIn->width = u_minify(config->info.width, level);
645 AddrSurfInfoIn->height = u_minify(config->info.height, level);
650 if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
660 assert(config->info.levels == 1);
668 if (config->is_3d)
669 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
670 else if (config->is_cube)
673 AddrSurfInfoIn->numSlices = config->info.array_size;
770 (prev_level_clearable && level == config->info.levels - 1))
779 surf->meta_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
785 if (config->info.array_size > 1) {
867 static bool get_display_flag(const struct ac_surf_config *config, const struct radeon_surf *surf)
869 unsigned num_channels = config->info.num_channels;
879 if (!config->is_1d && !config->is_3d && !config->is_cube &&
881 surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 &&
901 * Copy surface-global settings like pipe/bank config from level 0 surface
905 const struct ac_surf_config *config,
926 if ((info->gfx_level >= GFX7 || config->info.levels == 1) && config->info.surf_index &&
929 !get_display_flag(config, surf)) {
936 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
953 static void ac_compute_cmask(const struct radeon_info *info, const struct ac_surf_config *config,
961 (config->info.samples >= 2 && !surf->fmask_size))
1002 if (config->is_3d)
1003 num_layers = config->info.depth;
1004 else if (config->is_cube)
1007 num_layers = config->info.array_size;
1015 * Fill in the tiling information in \p surf based on the given surface config.
1021 const struct ac_surf_config *config, enum radeon_surf_mode mode,
1047 if (config->info.samples > 1)
1093 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1097 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1110 AddrSurfInfoIn.flags.cube = config->is_cube;
1111 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1112 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
1120 !AddrSurfInfoIn.flags.fmask && config->info.samples <= 1 &&
1133 ((config->info.array_size == 1 && config->info.depth == 1) || config->info.levels == 1);
1158 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
1235 for (level = 0; level < config->info.levels; level++) {
1236 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn,
1258 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1274 for (level = 0; level < config->info.levels; level++) {
1275 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn,
1290 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1304 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color && info->has_graphics &&
1315 fin.height = config->info.height;
1340 if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) {
1348 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1367 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_size && config->info.levels > 1) {
1383 surf->meta_size && config->info.levels > 1) {
1410 ac_compute_cmask(info, config, surf);
1558 const struct ac_surf_config *config)
1567 return config->info.width > 2560 || config->info.height > 2560;
1591 const struct ac_surf_config *config,
1627 return (!gfx10_DCN_requires_independent_64B_blocks(info, config) ||
1709 const struct ac_surf_config *config, struct radeon_surf *surf,
1859 if (config->info.surf_index && in->swizzleMode >= ADDR_SW_64KB_Z_T && !out.mipChainInTail &&
1867 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1890 is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned,
2053 if (config->info.fmask_surf_index && fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
2062 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
2135 const struct ac_surf_config *config, enum radeon_surf_mode mode,
2194 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
2200 AddrSurfInfoIn.numMipLevels = config->info.levels;
2201 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
2205 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
2210 if (config->is_3d)
2212 else if (info->gfx_level != GFX9 && config->is_1d)
2217 AddrSurfInfoIn.width = config->info.width;
2218 AddrSurfInfoIn.height = config->info.height;
2220 if (config->is_3d)
2221 AddrSurfInfoIn.numSlices = config->info.depth;
2222 else if (config->is_cube)
2225 AddrSurfInfoIn.numSlices = config->info.array_size;
2280 gfx10_DCN_requires_independent_64B_blocks(info, config))) {
2292 assert(config->info.samples <= 1);
2342 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2361 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2371 if (!config->is_3d && !config->is_cube) {
2380 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2397 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2402 if (info->has_graphics && !compressed && !config->is_3d && config->info.levels == 1 &&
2408 is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2488 const struct ac_surf_config *config, enum radeon_surf_mode mode,
2493 r = surf_config_sanity(config, surf->flags);
2498 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
2500 r = gfx6_compute_surface(addrlib->handle, info, config, mode, surf);
2513 assert(config->info.samples >= 2);
2520 if (surf->cmask_size && config->info.samples >= 2) {
2531 (info->gfx_level >= GFX9 || !get_display_flag(config, surf))) {