Lines Matching defs:AddrSurfInfoIn
632 bool compressed, ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
643 AddrSurfInfoIn->mipLevel = level;
644 AddrSurfInfoIn->width = u_minify(config->info.width, level);
645 AddrSurfInfoIn->height = u_minify(config->info.height, level);
650 if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
651 AddrSurfInfoIn->bpp && util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
652 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
654 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
659 if (AddrSurfInfoIn->bpp == 96) {
661 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
665 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
669 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
671 AddrSurfInfoIn->numSlices = 6;
673 AddrSurfInfoIn->numSlices = config->info.array_size;
679 AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x;
681 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
685 AddrSurfInfoIn->basePitch *= surf->blk_w;
688 ret = AddrComputeSurfaceInfo(addrlib, AddrSurfInfoIn, AddrSurfInfoOut);
721 if (AddrSurfInfoIn->flags.prt) {
737 if (!AddrSurfInfoIn->flags.depth && !AddrSurfInfoIn->flags.stencil)
741 if (AddrSurfInfoIn->flags.dccCompatible && (level == 0 || AddrDccOut->subLvlCompressible)) {
817 if (!is_stencil && AddrSurfInfoIn->flags.depth && surf_level->mode == RADEON_SURF_MODE_2D &&
1026 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1036 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
1057 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
1061 AddrSurfInfoIn.tileMode = ADDR_TM_PRT_TILED_THIN1;
1063 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
1067 AddrSurfInfoIn.tileMode = ADDR_TM_PRT_2D_TILED_THIN1;
1069 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
1081 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1084 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1090 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
1093 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1094 AddrSurfInfoIn.tileIndex = -1;
1097 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1102 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
1104 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
1106 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
1108 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1109 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1110 AddrSurfInfoIn.flags.cube = config->is_cube;
1111 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1112 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
1113 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
1114 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
1119 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
1120 !AddrSurfInfoIn.flags.fmask && config->info.samples <= 1 &&
1129 AddrSurfInfoIn.flags.dccCompatible =
1135 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
1136 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1157 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
1162 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
1165 AddrSurfInfoIn.flags.noStencil = 1;
1171 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw &&
1181 AddrSurfInfoIn.flags.opt4Space = 0;
1182 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
1184 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
1193 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
1196 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
1198 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
1200 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
1203 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
1205 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
1207 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
1209 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
1213 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
1214 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
1216 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
1236 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn,
1246 AddrSurfInfoIn.flags.tcCompatible = 0;
1250 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
1251 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
1252 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
1266 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
1267 AddrSurfInfoIn.bpp = 8;
1268 AddrSurfInfoIn.flags.depth = 0;
1269 AddrSurfInfoIn.flags.stencil = 1;
1270 AddrSurfInfoIn.flags.tcCompatible = 0;
1271 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
1275 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn,
1304 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color && info->has_graphics &&
1316 fin.numSlices = AddrSurfInfoIn.numSlices;
1317 fin.numSamples = AddrSurfInfoIn.numSamples;
1318 fin.numFrags = AddrSurfInfoIn.numFrags;
2139 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
2142 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
2151 AddrSurfInfoIn.format = ADDR_FMT_BC1;
2154 AddrSurfInfoIn.format = ADDR_FMT_BC3;
2163 AddrSurfInfoIn.format = ADDR_FMT_8;
2167 AddrSurfInfoIn.format = ADDR_FMT_16;
2171 AddrSurfInfoIn.format = ADDR_FMT_32;
2175 AddrSurfInfoIn.format = ADDR_FMT_32_32;
2179 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
2183 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
2188 AddrSurfInfoIn.bpp = surf->bpe * 8;
2192 AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
2193 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
2194 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
2196 AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
2197 AddrSurfInfoIn.flags.opt4space = 1;
2198 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
2200 AddrSurfInfoIn.numMipLevels = config->info.levels;
2201 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
2202 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
2205 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
2211 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
2213 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
2215 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
2217 AddrSurfInfoIn.width = config->info.width;
2218 AddrSurfInfoIn.height = config->info.height;
2221 AddrSurfInfoIn.numSlices = config->info.depth;
2223 AddrSurfInfoIn.numSlices = 6;
2225 AddrSurfInfoIn.numSlices = config->info.array_size;
2228 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
2229 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
2232 ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
2233 } else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) {
2248 if (AddrSurfInfoIn.flags.display) {
2257 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
2258 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
2294 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
2301 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode;
2305 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2306 &AddrSurfInfoIn.swizzleMode);
2321 AddrSurfInfoIn.swizzleMode = ac_modifier_gfx9_swizzle_mode(surf->modifier);
2324 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
2333 if (AddrSurfInfoIn.flags.stencil)
2342 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2349 AddrSurfInfoIn.flags.stencil = 1;
2350 AddrSurfInfoIn.bpp = 8;
2351 AddrSurfInfoIn.format = ADDR_FMT_8;
2353 if (!AddrSurfInfoIn.flags.depth) {
2354 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2355 &AddrSurfInfoIn.swizzleMode);
2359 AddrSurfInfoIn.flags.depth = 0;
2361 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2389 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
2394 if (AddrSurfInfoIn.flags.color)
2396 if (AddrSurfInfoIn.flags.display && surf->modifier == DRM_FORMAT_MOD_INVALID) {
2403 AddrSurfInfoIn.flags.color && !surf->is_linear &&
2412 AddrSurfInfoIn.flags.display && surf->bpe == 4) {
2417 if (!AddrSurfInfoIn.flags.display)