Lines Matching refs:info
135 /** video memory type info*/
268 *info)
280 struct drm_amdgpu_info_hw_ip *info)
285 uint32_t flags, struct amdgpu_heap_info *info)
290 struct amdgpu_gpu_info *info)
299 static int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
342 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
344 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
405 has_tmz_support(amdgpu_device_handle dev, struct radeon_info *info, uint32_t ids_flags)
415 if (info->drm_minor >= 40)
419 if (info->gfx_level < GFX9)
422 if (info->drm_minor < 36)
436 static void set_custom_cu_en_mask(struct radeon_info *info)
438 info->spi_cu_en = ~0;
537 spi_cu_en &= BITFIELD_MASK(info->max_good_cu_per_sa);
544 if (info->has_graphics) {
545 uint32_t min_full_cu_mask = BITFIELD_MASK(info->min_good_cu_per_sa);
558 ac_compute_late_alloc(info, false, false, false, &unused, &cu_mask_ge);
576 info->spi_cu_en = spi_cu_en;
577 info->spi_cu_en_has_effect = spi_cu_en & BITFIELD_MASK(info->max_good_cu_per_sa);
582 bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
602 /* Get PCI info. */
608 info->pci_domain = devinfo->businfo.pci->domain;
609 info->pci_bus = devinfo->businfo.pci->bus;
610 info->pci_dev = devinfo->businfo.pci->dev;
611 info->pci_func = devinfo->businfo.pci->func;
614 assert(info->drm_major == 3);
615 info->is_amdgpu = true;
617 if (info->drm_minor < 15) {
620 info->drm_major, info->drm_minor, info->drm_patchlevel);
651 if (info->drm_minor >= 48 && ip_info.ip_discovery_version) {
652 info->ip[ip_type].ver_major = (ip_info.ip_discovery_version >> 16) & 0xff;
653 info->ip[ip_type].ver_minor = (ip_info.ip_discovery_version >> 8) & 0xff;
655 info->ip[ip_type].ver_major = ip_info.hw_ip_version_major;
656 info->ip[ip_type].ver_minor = ip_info.hw_ip_version_minor;
663 info->ip[AMD_IP_GFX].ver_minor = info->ip[AMD_IP_COMPUTE].ver_minor = 1;
669 info->ip[AMD_IP_GFX].ver_minor = info->ip[AMD_IP_COMPUTE].ver_minor = 3;
671 info->ip[ip_type].num_queues = util_bitcount(ip_info.available_rings);
672 info->ib_alignment = MAX3(info->ib_alignment, ip_info.ib_start_alignment,
677 if (!info->ip[AMD_IP_GFX].num_queues && !info->ip[AMD_IP_COMPUTE].num_queues) {
682 assert(util_is_power_of_two_or_zero(info->ip[AMD_IP_COMPUTE].num_queues));
683 assert(util_is_power_of_two_or_zero(info->ip[AMD_IP_SDMA].num_queues));
689 info->ib_alignment = MAX2(info->ib_alignment, 1024);
691 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version,
692 &info->me_fw_feature);
698 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_MEC, 0, 0, &info->mec_fw_version,
699 &info->mec_fw_feature);
705 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0, &info->pfp_fw_version,
706 &info->pfp_fw_feature);
724 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
739 info->gart_size_kb = DIV_ROUND_UP(meminfo.gtt.total_heap_size, 1024);
740 info->vram_size_kb = DIV_ROUND_UP(fix_vram_size(meminfo.vram.total_heap_size), 1024);
741 info->vram_vis_size_kb = DIV_ROUND_UP(meminfo.cpu_accessible_vram.total_heap_size, 1024);
743 if (info->drm_minor >= 41) {
745 sizeof(info->dec_caps), &(info->dec_caps));
747 sizeof(info->enc_caps), &(info->enc_caps));
751 info->all_vram_visible = info->vram_size_kb * 0.9 < info->vram_vis_size_kb;
754 info->pci_id = device_info.device_id;
755 info->pci_rev_id = device_info.pci_rev;
756 info->vce_harvest_config = device_info.vce_harvest_config;
760 info->family = CHIP_##chipname; \
761 info->name = #chipname; \
839 if (!info->name) {
845 memset(info->lowercase_name, 0, sizeof(info->lowercase_name));
846 for (unsigned i = 0; info->name[i] && i < ARRAY_SIZE(info->lowercase_name) - 1; i++)
847 info->lowercase_name[i] = tolower(info->name[i]);
849 if (info->ip[AMD_IP_GFX].ver_major == 11)
850 info->gfx_level = GFX11;
851 else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 3)
852 info->gfx_level = GFX10_3;
853 else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 1)
854 info->gfx_level = GFX10;
855 else if (info->ip[AMD_IP_GFX].ver_major == 9 || info->ip[AMD_IP_COMPUTE].ver_major == 9)
856 info->gfx_level = GFX9;
857 else if (info->ip[AMD_IP_GFX].ver_major == 8)
858 info->gfx_level = GFX8;
859 else if (info->ip[AMD_IP_GFX].ver_major == 7)
860 info->gfx_level = GFX7;
861 else if (info->ip[AMD_IP_GFX].ver_major == 6)
862 info->gfx_level = GFX6;
865 info->ip[AMD_IP_GFX].ver_major, info->ip[AMD_IP_GFX].ver_minor);
869 info->smart_access_memory = info->all_vram_visible &&
870 info->gfx_level >= GFX10_3 &&
874 info->family_id = device_info.family;
875 info->chip_external_rev = device_info.external_rev;
876 info->chip_rev = device_info.chip_rev;
877 info->marketing_name = amdgpu_get_marketing_name(dev);
878 info->is_pro_graphics = info->marketing_name && (strstr(info->marketing_name, "Pro") ||
879 strstr(info->marketing_name, "PRO") ||
880 strstr(info->marketing_name, "Frontier"));
883 info->has_dedicated_vram = !(device_info.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
888 if (info->has_dedicated_vram)
889 info->max_heap_size_kb = info->vram_size_kb;
891 info->max_heap_size_kb = info->gart_size_kb;
893 info->vram_type = device_info.vram_type;
894 info->memory_bus_width = device_info.vram_bit_width;
897 info->has_l2_uncached = info->gfx_level >= GFX9;
901 info->max_gpu_freq_mhz = device_info.max_engine_clock / 1000;
902 info->memory_freq_mhz_effective = info->memory_freq_mhz = device_info.max_memory_clock / 1000;
903 info->max_tcc_blocks = device_info.num_tcc_blocks;
904 info->max_se = device_info.num_shader_engines;
905 info->max_sa_per_se = device_info.num_shader_arrays_per_engine;
906 info->uvd_fw_version = info->ip[AMD_IP_UVD].num_queues ? uvd_version : 0;
907 info->vce_fw_version = info->ip[AMD_IP_VCE].num_queues ? vce_version : 0;
910 switch (info->vram_type) {
915 info->memory_freq_mhz_effective *= 2;
919 info->memory_freq_mhz_effective *= 4;
922 info->memory_freq_mhz_effective *= 16;
927 info->has_video_hw.vcn_decode
928 = info->family >= CHIP_GFX1100
929 ? info->ip[AMD_IP_VCN_UNIFIED].num_queues != 0
930 : info->ip[AMD_IP_VCN_DEC].num_queues != 0;
931 info->has_userptr = true;
932 info->has_syncobj = has_syncobj(fd);
933 info->has_timeline_syncobj = has_timeline_syncobj(fd);
934 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
935 info->has_local_buffers = info->drm_minor >= 20;
936 info->has_bo_metadata = true;
937 info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
941 info->has_sparse_vm_mappings = info->gfx_level >= GFX7;
942 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
943 info->mid_command_buffer_preemption_enabled = device_info.ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
944 info->has_tmz_support = has_tmz_support(dev, info, device_info.ids_flags);
945 info->kernel_has_modifiers = has_modifiers(fd);
946 info->has_graphics = info->ip[AMD_IP_GFX].num_queues > 0;
948 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
949 info->max_render_backends = device_info.num_rb_pipes;
951 if (info->family == CHIP_KAVERI)
952 info->max_render_backends = 2;
954 info->clock_crystal_freq = device_info.gpu_counter_freq;
955 if (!info->clock_crystal_freq) {
957 info->clock_crystal_freq = 1;
959 if (info->gfx_level >= GFX10) {
960 info->tcc_cache_line_size = 128;
962 if (info->drm_minor >= 35) {
963 info->num_tcc_blocks = info->max_tcc_blocks - util_bitcount64(device_info.tcc_disabled_mask);
966 info->num_tcc_blocks = info->vram_size_kb / (512 * 1024);
967 if (info->num_tcc_blocks > info->max_tcc_blocks)
968 info->num_tcc_blocks /= 2;
971 if (!info->has_graphics && info->family >= CHIP_ALDEBARAN)
972 info->tcc_cache_line_size = 128;
974 info->tcc_cache_line_size = 64;
976 info->num_tcc_blocks = info->max_tcc_blocks;
979 info->tcc_rb_non_coherent = !util_is_power_of_two_or_zero(info->num_tcc_blocks);
981 switch (info->family) {
990 info->l2_cache_size = info->num_tcc_blocks * 64 * 1024;
1001 info->l2_cache_size = info->num_tcc_blocks * 128 * 1024;
1004 info->l2_cache_size = info->num_tcc_blocks * 256 * 1024;
1007 info->l2_cache_size = info->num_tcc_blocks * 512 * 1024;
1011 info->l1_cache_size = 16384;
1013 info->mc_arb_ramcfg = amdinfo.mc_arb_ramcfg;
1014 info->gb_addr_config = amdinfo.gb_addr_cfg;
1015 if (info->gfx_level >= GFX9) {
1016 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(info->gb_addr_config);
1017 info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
1019 info->num_tile_pipes = cik_get_num_tile_pipes(&amdinfo);
1020 info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config);
1022 info->r600_has_virtual_memory = true;
1029 info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024;
1033 info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4;
1034 info->lds_alloc_granularity = info->gfx_level >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity;
1037 info->ib_pad_dw_mask[AMD_IP_GFX] = 0xff;
1038 info->ib_pad_dw_mask[AMD_IP_COMPUTE] = 0xff;
1039 info->ib_pad_dw_mask[AMD_IP_SDMA] = 0xf;
1040 info->ib_pad_dw_mask[AMD_IP_UVD] = 0xf;
1041 info->ib_pad_dw_mask[AMD_IP_VCE] = 0x3f;
1042 info->ib_pad_dw_mask[AMD_IP_UVD_ENC] = 0x3f;
1043 info->ib_pad_dw_mask[AMD_IP_VCN_DEC] = 0xf;
1044 info->ib_pad_dw_mask[AMD_IP_VCN_ENC] = 0x3f;
1045 info->ib_pad_dw_mask[AMD_IP_VCN_JPEG] = 0xf;
1051 info->has_clear_state = info->gfx_level >= GFX7;
1053 info->has_distributed_tess =
1054 info->gfx_level >= GFX10 || (info->gfx_level >= GFX8 && info->max_se >= 2);
1056 info->has_dcc_constant_encode =
1057 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10;
1059 info->has_rbplus = info->family == CHIP_STONEY || info->gfx_level >= GFX9;
1064 info->rbplus_allowed =
1065 info->has_rbplus &&
1066 (info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN ||
1067 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10_3);
1069 info->has_out_of_order_rast =
1070 info->gfx_level >= GFX8 && info->gfx_level <= GFX9 && info->max_se >= 2;
1073 info->has_packed_math_16bit = info->gfx_level >= GFX9;
1078 info->has_accelerated_dot_product =
1079 info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN ||
1080 info->family == CHIP_VEGA20 || info->family >= CHIP_NAVI12;
1083 info->has_load_ctx_reg_pkt =
1084 info->gfx_level >= GFX9 || (info->gfx_level >= GFX8 && info->me_fw_feature >= 41);
1086 info->cpdma_prefetch_writes_memory = info->gfx_level <= GFX8;
1088 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
1090 info->has_tc_compat_zrange_bug = info->gfx_level >= GFX8 && info->gfx_level <= GFX9;
1092 info->has_msaa_sample_loc_bug =
1093 (info->family >= CHIP_POLARIS10 && info->family <= CHIP_POLARIS12) ||
1094 info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
1096 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
1099 info->has_zero_index_buffer_bug = info->gfx_level == GFX10;
1104 info->has_image_load_dcc_bug = info->family == CHIP_NAVI23 ||
1105 info->family == CHIP_VANGOGH ||
1106 info->family == CHIP_REMBRANDT;
1111 info->has_two_planes_iterate256_bug = info->gfx_level == GFX10;
1114 info->has_vgt_flush_ngg_legacy_bug = info->gfx_level == GFX10 ||
1115 info->family == CHIP_NAVI21;
1125 info->has_cs_regalloc_hang_bug = info->gfx_level == GFX6 ||
1126 info->family == CHIP_BONAIRE ||
1127 info->family == CHIP_KABINI;
1132 info->has_32bit_predication = (info->gfx_level >= GFX10 &&
1133 info->me_fw_feature >= 32) ||
1134 (info->gfx_level == GFX9 &&
1135 info->me_fw_feature >= 52);
1137 info->has_export_conflict_bug = info->gfx_level == GFX11;
1140 info->num_cu = 0;
1141 for (i = 0; i < info->max_se; i++) {
1142 for (j = 0; j < info->max_sa_per_se; j++) {
1143 if (info->gfx_level >= GFX11) {
1144 assert(info->max_sa_per_se <= 2);
1145 info->cu_mask[i][j] = device_info.cu_bitmap[i % 4][(i / 4) * 2 + j];
1146 } else if (info->family == CHIP_ARCTURUS) {
1147 /* The CU bitmap in amd gpu info structure is
1158 assert(info->max_sa_per_se == 1);
1159 info->cu_mask[i][0] = device_info.cu_bitmap[i % 4][i / 4];
1161 info->cu_mask[i][j] = device_info.cu_bitmap[i][j];
1163 info->num_cu += util_bitcount(info->cu_mask[i][j]);
1168 if (info->gfx_level >= GFX10_3 && info->max_se > 1) {
1169 info->num_se = 0;
1171 for (unsigned se = 0; se < info->max_se; se++) {
1172 for (unsigned sa = 0; sa < info->max_sa_per_se; sa++) {
1173 if (info->cu_mask[se][sa]) {
1174 info->num_se++;
1181 info->num_se = info->max_se;
1187 unsigned cu_group = info->gfx_level >= GFX10 ? 2 : 1;
1188 info->max_good_cu_per_sa =
1189 DIV_ROUND_UP(info->num_cu, (info->num_se * info->max_sa_per_se * cu_group)) *
1191 info->min_good_cu_per_sa =
1192 (info->num_cu / (info->num_se * info->max_sa_per_se * cu_group)) * cu_group;
1194 memcpy(info->si_tile_mode_array, amdinfo.gb_tile_mode, sizeof(amdinfo.gb_tile_mode));
1195 info->enabled_rb_mask = amdinfo.enabled_rb_pipes_mask;
1197 memcpy(info->cik_macrotile_mode_array, amdinfo.gb_macro_tile_mode,
1200 info->pte_fragment_size = alignment_info.size_local;
1201 info->gart_page_size = alignment_info.size_remote;
1203 if (info->gfx_level == GFX6)
1204 info->gfx_ib_pad_with_type2 = true;
1207 if (info->gfx_level >= GFX9)
1208 info->ib_alignment = MAX2(info->ib_alignment, info->tcc_cache_line_size);
1210 if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 ||
1211 info->family == CHIP_RENOIR)) ||
1212 info->gfx_level >= GFX10_3) {
1214 if (info->max_render_backends == 1 && info->gfx_level == GFX9)
1215 info->use_display_dcc_unaligned = true;
1217 info->use_display_dcc_with_retile_blit = true;
1220 info->has_stable_pstate = info->drm_minor >= 45;
1222 if (info->gfx_level >= GFX11) {
1223 info->pc_lines = 1024;
1224 info->pbb_max_alloc_count = 255; /* minimum is 2, maximum is 256 */
1225 } else if (info->gfx_level >= GFX9 && info->has_graphics) {
1228 switch (info->family) {
1257 info->pc_lines = pc_lines;
1259 if (info->gfx_level >= GFX10) {
1260 info->pbb_max_alloc_count = pc_lines / 3;
1262 info->pbb_max_alloc_count = MIN2(128, pc_lines / (4 * info->max_se));
1266 if (info->gfx_level >= GFX10_3)
1267 info->max_wave64_per_simd = 16;
1268 else if (info->gfx_level == GFX10)
1269 info->max_wave64_per_simd = 20;
1270 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
1271 info->max_wave64_per_simd = 8;
1273 info->max_wave64_per_simd = 10;
1275 if (info->gfx_level >= GFX10) {
1276 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
1277 info->min_sgpr_alloc = 128;
1278 info->sgpr_alloc_granularity = 128;
1279 } else if (info->gfx_level >= GFX8) {
1280 info->num_physical_sgprs_per_simd = 800;
1281 info->min_sgpr_alloc = 16;
1282 info->sgpr_alloc_granularity = 16;
1284 info->num_physical_sgprs_per_simd = 512;
1285 info->min_sgpr_alloc = 8;
1286 info->sgpr_alloc_granularity = 8;
1289 info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS;
1290 info->never_stop_sq_perf_counters = info->gfx_level == GFX10 ||
1291 info->gfx_level == GFX10_3;
1292 info->never_send_perfcounter_stop = info->gfx_level == GFX11;
1293 info->has_sqtt_rb_harvest_bug = (info->family == CHIP_NAVI23 ||
1294 info->family == CHIP_NAVI24 ||
1295 info->family == CHIP_REMBRANDT ||
1296 info->family == CHIP_VANGOGH) &&
1297 util_bitcount(info->enabled_rb_mask) !=
1298 info->max_render_backends;
1301 info->has_sqtt_auto_flush_mode_bug = info->gfx_level == GFX10_3;
1303 info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
1305 if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) {
1306 info->min_wave64_vgpr_alloc = 8;
1307 info->max_vgpr_alloc = 512;
1308 info->wave64_vgpr_alloc_granularity = 8;
1310 info->min_wave64_vgpr_alloc = 4;
1311 info->max_vgpr_alloc = 256;
1312 info->wave64_vgpr_alloc_granularity = 4;
1315 info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256;
1316 info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4;
1321 info->discardable_allows_big_page = info->gfx_level >= GFX10_3 &&
1322 info->has_dedicated_vram &&
1323 info->drm_minor >= 47;
1331 info->max_scratch_waves = MAX2(32 * info->min_good_cu_per_sa * info->max_sa_per_se * info->num_se,
1333 info->num_rb = util_bitcount(info->enabled_rb_mask);
1334 info->max_gflops = info->num_cu * 128 * info->max_gpu_freq_mhz / 1000;
1335 info->memory_bandwidth_gbps = DIV_ROUND_UP(info->memory_freq_mhz_effective * info->memory_bus_width / 8, 1000);
1337 if (info->gfx_level >= GFX10_3 && info->has_dedicated_vram) {
1338 info->l3_cache_size_mb = info->num_tcc_blocks *
1339 (info->family == CHIP_NAVI21 ||
1340 info->family == CHIP_NAVI22 ? 8 : 4);
1343 set_custom_cu_en_mask(info);
1361 ac_parse_ib(stdout, ib, size / 4, NULL, 0, "IB", info->gfx_level, NULL, NULL);
1379 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
1386 * Use the device info directly instead of using a sha1. GL/VK UUIDs
1391 uint_uuid[0] = info->pci_domain;
1392 uint_uuid[1] = info->pci_bus;
1393 uint_uuid[2] = info->pci_dev;
1394 uint_uuid[3] = info->pci_func;
1397 void ac_print_gpu_info(struct radeon_info *info, FILE *f)
1399 fprintf(f, "Device info:\n");
1400 fprintf(f, " name = %s\n", info->name);
1401 fprintf(f, " marketing_name = %s\n", info->marketing_name);
1402 fprintf(f, " num_se = %i\n", info->num_se);
1403 fprintf(f, " num_rb = %i\n", info->num_rb);
1404 fprintf(f, " num_cu = %i\n", info->num_cu);
1405 fprintf(f, " max_gpu_freq = %i MHz\n", info->max_gpu_freq_mhz);
1406 fprintf(f, " max_gflops = %u GFLOPS\n", info->max_gflops);
1408 if (info->gfx_level >= GFX10) {
1409 fprintf(f, " l0_cache_size = %i KB\n", DIV_ROUND_UP(info->l1_cache_size, 1024));
1412 fprintf(f, " l1_cache_size = %i KB\n", DIV_ROUND_UP(info->l1_cache_size, 1024));
1415 fprintf(f, " l2_cache_size = %i KB\n", DIV_ROUND_UP(info->l2_cache_size, 1024));
1417 if (info->l3_cache_size_mb)
1418 fprintf(f, " l3_cache_size = %i MB\n", info->l3_cache_size_mb);
1420 fprintf(f, " memory_channels = %u (TCC blocks)\n", info->num_tcc_blocks);
1422 DIV_ROUND_UP(info->vram_size_kb, (1024 * 1024)),
1423 DIV_ROUND_UP(info->vram_size_kb, 1024));
1424 fprintf(f, " memory_freq = %u GHz\n", DIV_ROUND_UP(info->memory_freq_mhz_effective, 1000));
1425 fprintf(f, " memory_bus_width = %u bits\n", info->memory_bus_width);
1426 fprintf(f, " memory_bandwidth = %u GB/s\n", info->memory_bandwidth_gbps);
1427 fprintf(f, " clock_crystal_freq = %i KHz\n", info->clock_crystal_freq);
1437 [AMD_IP_VCN_ENC] = info->family >= CHIP_GFX1100 ? "VCN" : "VCN_ENC",
1442 if (info->ip[i].num_queues) {
1444 info->ip[i].ver_major, info->ip[i].ver_minor, info->ip[i].num_queues);
1449 fprintf(f, " pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", info->pci_domain, info->pci_bus,
1450 info->pci_dev, info->pci_func);
1451 fprintf(f, " pci_id = 0x%x\n", info->pci_id);
1452 fprintf(f, " pci_rev_id = 0x%x\n", info->pci_rev_id);
1453 fprintf(f, " family = %i\n", info->family);
1454 fprintf(f, " gfx_level = %i\n", info->gfx_level);
1455 fprintf(f, " family_id = %i\n", info->family_id);
1456 fprintf(f, " chip_external_rev = %i\n", info->chip_external_rev);
1457 fprintf(f, " chip_rev = %i\n", info->chip_rev);
1460 fprintf(f, " is_pro_graphics = %u\n", info->is_pro_graphics);
1461 fprintf(f, " has_graphics = %i\n", info->has_graphics);
1462 fprintf(f, " has_clear_state = %u\n", info->has_clear_state);
1463 fprintf(f, " has_distributed_tess = %u\n", info->has_distributed_tess);
1464 fprintf(f, " has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
1465 fprintf(f, " has_rbplus = %u\n", info->has_rbplus);
1466 fprintf(f, " rbplus_allowed = %u\n", info->rbplus_allowed);
1467 fprintf(f, " has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
1468 fprintf(f, " has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
1469 fprintf(f, " cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
1470 fprintf(f, " has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
1471 fprintf(f, " has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
1472 fprintf(f, " has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
1473 fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
1474 fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication);
1475 fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
1476 fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
1477 fprintf(f, " has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug);
1478 fprintf(f, " has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug);
1479 fprintf(f, " never_send_perfcounter_stop = %i\n", info->never_send_perfcounter_stop);
1480 fprintf(f, " discardable_allows_big_page = %i\n", info->discardable_allows_big_page);
1483 fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
1484 fprintf(f, " use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
1486 fprintf(f, "Memory info:\n");
1487 fprintf(f, " pte_fragment_size = %u\n", info->pte_fragment_size);
1488 fprintf(f, " gart_page_size = %u\n", info->gart_page_size);
1489 fprintf(f, " gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size_kb, 1024));
1490 fprintf(f, " vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size_kb, 1024));
1491 fprintf(f, " vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size_kb, 1024));
1492 fprintf(f, " vram_type = %i\n", info->vram_type);
1493 fprintf(f, " max_heap_size_kb = %i MB\n", (int)DIV_ROUND_UP(info->max_heap_size_kb, 1024));
1494 fprintf(f, " min_alloc_size = %u\n", info->min_alloc_size);
1495 fprintf(f, " address32_hi = 0x%x\n", info->address32_hi);
1496 fprintf(f, " has_dedicated_vram = %u\n", info->has_dedicated_vram);
1497 fprintf(f, " all_vram_visible = %u\n", info->all_vram_visible);
1498 fprintf(f, " smart_access_memory = %u\n", info->smart_access_memory);
1499 fprintf(f, " max_tcc_blocks = %i\n", info->max_tcc_blocks);
1500 fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
1501 fprintf(f, " tcc_rb_non_coherent = %u\n", info->tcc_rb_non_coherent);
1502 fprintf(f, " pc_lines = %u\n", info->pc_lines);
1503 fprintf(f, " lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
1504 fprintf(f, " lds_alloc_granularity = %i\n", info->lds_alloc_granularity);
1505 fprintf(f, " lds_encode_granularity = %i\n", info->lds_encode_granularity);
1506 fprintf(f, " max_memory_clock = %i MHz\n", info->memory_freq_mhz);
1508 fprintf(f, "CP info:\n");
1509 fprintf(f, " gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
1510 fprintf(f, " ib_alignment = %u\n", info->ib_alignment);
1511 fprintf(f, " me_fw_version = %i\n", info->me_fw_version);
1512 fprintf(f, " me_fw_feature = %i\n", info->me_fw_feature);
1513 fprintf(f, " mec_fw_version = %i\n", info->mec_fw_version);
1514 fprintf(f, " mec_fw_feature = %i\n", info->mec_fw_feature);
1515 fprintf(f, " pfp_fw_version = %i\n", info->pfp_fw_version);
1516 fprintf(f, " pfp_fw_feature = %i\n", info->pfp_fw_feature);
1518 fprintf(f, "Multimedia info:\n");
1519 fprintf(f, " vce_encode = %u\n", info->ip[AMD_IP_VCE].num_queues);
1521 if (info->family >= CHIP_GFX1100)
1522 fprintf(f, " vcn_unified = %u\n", info->has_video_hw.vcn_decode);
1524 fprintf(f, " vcn_decode = %u\n", info->has_video_hw.vcn_decode);
1525 fprintf(f, " vcn_encode = %u\n", info->ip[AMD_IP_VCN_ENC].num_queues);
1528 fprintf(f, " uvd_fw_version = %u\n", info->uvd_fw_version);
1529 fprintf(f, " vce_fw_version = %u\n", info->vce_fw_version);
1530 fprintf(f, " vce_harvest_config = %i\n", info->vce_harvest_config);
1533 fprintf(f, " drm = %i.%i.%i\n", info->drm_major, info->drm_minor, info->drm_patchlevel);
1534 fprintf(f, " has_userptr = %i\n", info->has_userptr);
1535 fprintf(f, " has_syncobj = %u\n", info->has_syncobj);
1536 fprintf(f, " has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
1537 fprintf(f, " has_fence_to_handle = %u\n", info->has_fence_to_handle);
1538 fprintf(f, " has_local_buffers = %u\n", info->has_local_buffers);
1539 fprintf(f, " has_bo_metadata = %u\n", info->has_bo_metadata);
1540 fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
1541 fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
1542 fprintf(f, " has_stable_pstate = %u\n", info->has_stable_pstate);
1543 fprintf(f, " has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
1545 info->mid_command_buffer_preemption_enabled);
1546 fprintf(f, " has_tmz_support = %u\n", info->has_tmz_support);
1548 fprintf(f, "Shader core info:\n");
1549 for (unsigned i = 0; i < info->max_se; i++) {
1550 for (unsigned j = 0; j < info->max_sa_per_se; j++) {
1552 info->cu_mask[i][j], util_bitcount(info->cu_mask[i][j]),
1553 info->spi_cu_en & BITFIELD_MASK(util_bitcount(info->cu_mask[i][j])));
1556 fprintf(f, " spi_cu_en_has_effect = %i\n", info->spi_cu_en_has_effect);
1557 fprintf(f, " max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
1558 fprintf(f, " min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
1559 fprintf(f, " max_se = %i\n", info->max_se);
1560 fprintf(f, " max_sa_per_se = %i\n", info->max_sa_per_se);
1561 fprintf(f, " max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
1562 fprintf(f, " num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
1564 info->num_physical_wave64_vgprs_per_simd);
1565 fprintf(f, " num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit);
1566 fprintf(f, " min_sgpr_alloc = %i\n", info->min_sgpr_alloc);
1567 fprintf(f, " max_sgpr_alloc = %i\n", info->max_sgpr_alloc);
1568 fprintf(f, " sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
1569 fprintf(f, " min_wave64_vgpr_alloc = %i\n", info->min_wave64_vgpr_alloc);
1570 fprintf(f, " max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
1571 fprintf(f, " wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
1572 fprintf(f, " max_scratch_waves = %i\n", info->max_scratch_waves);
1574 fprintf(f, "Render backend info:\n");
1575 fprintf(f, " pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
1576 fprintf(f, " max_render_backends = %i\n", info->max_render_backends);
1577 fprintf(f, " num_tile_pipes = %i\n", info->num_tile_pipes);
1578 fprintf(f, " pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
1579 fprintf(f, " enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
1580 fprintf(f, " max_alignment = %u\n", (unsigned)info->max_alignment);
1581 fprintf(f, " pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
1583 fprintf(f, "GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
1584 if (info->gfx_level >= GFX10) {
1585 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1587 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
1589 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1590 if (info->gfx_level >= GFX10_3)
1591 fprintf(f, " num_pkrs = %u\n", 1 << G_0098F8_NUM_PKRS(info->gb_addr_config));
1592 } else if (info->gfx_level == GFX9) {
1593 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1595 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
1597 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1599 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1600 fprintf(f, " num_banks = %u\n", 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
1602 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1604 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
1605 fprintf(f, " num_gpus = %u (raw)\n", G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
1607 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1608 fprintf(f, " num_rb_per_se = %u\n", 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
1609 fprintf(f, " row_size = %u\n", 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1610 fprintf(f, " num_lower_pipes = %u (raw)\n", G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1611 fprintf(f, " se_enable = %u (raw)\n", G_0098F8_SE_ENABLE(info->gb_addr_config));
1613 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1615 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
1617 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1619 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
1621 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1622 fprintf(f, " num_gpus = %u (raw)\n", G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
1624 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1625 fprintf(f, " row_size = %u\n", 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1626 fprintf(f, " num_lower_pipes = %u (raw)\n", G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1661 void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p,
1666 switch (info->family) {
1727 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
1733 if (info->family == CHIP_FIJI && info->cik_macrotile_mode_array[0] == 0x000000e8) {
1742 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
1750 void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config,
1753 unsigned sh_per_se = MAX2(info->max_sa_per_se, 1);
1754 unsigned num_se = MAX2(info->max_se, 1);
1755 unsigned rb_mask = info->enabled_rb_mask;
1756 unsigned num_rb = MIN2(info->max_render_backends, 16);
1771 if (info->gfx_level >= GFX7) {
1849 ac_get_compute_resource_limits(const struct radeon_info *info, unsigned waves_per_threadgroup,
1854 if (info->gfx_level >= GFX7) {
1855 unsigned num_cu_per_se = info->num_cu / info->num_se;
1858 if (info->gfx_level == GFX9 && !max_waves_per_sh) {
1859 max_waves_per_sh = info->max_good_cu_per_sa * info->num_simd_per_compute_unit *
1860 info->max_wave64_per_simd;
1883 void ac_get_hs_info(struct radeon_info *info,
1886 bool double_offchip_buffers = info->gfx_level >= GFX7 &&
1887 info->family != CHIP_CARRIZO &&
1888 info->family != CHIP_STONEY;
1895 info->family == CHIP_HAWAII ? 4096 : 8192;
1909 if (info->gfx_level >= GFX11) {
1911 } else if (info->gfx_level >= GFX10) {
1913 } else if (info->family == CHIP_VEGA12 || info->family == CHIP_VEGA20) {
1920 max_offchip_buffers = max_offchip_buffers_per_se * info->max_se;
1926 assert(info->family == CHIP_HAWAII);
1933 switch (info->gfx_level) {
1950 if (info->gfx_level >= GFX11) {
1954 } else if (info->gfx_level >= GFX10_3) {
1957 } else if (info->gfx_level >= GFX7) {
1958 if (info->gfx_level >= GFX8)
1968 hs->tess_factor_ring_size = 48 * 1024 * info->max_se;
1998 void ac_get_task_info(struct radeon_info *info,
2001 const uint16_t num_entries = get_task_num_entries(info->family);