Lines Matching refs:conf
42 const struct radeon_info *info, struct ac_shader_config *conf)
54 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
56 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
58 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
60 conf->float_mode = G_00B028_FLOAT_MODE(value);
61 conf->rsrc1 = value;
64 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
66 conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
67 conf->rsrc2 = value;
70 conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
71 conf->rsrc2 = value;
74 conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
75 conf->rsrc2 = value;
78 conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
79 conf->rsrc2 = value;
82 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
83 conf->rsrc2 = value;
86 conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
87 conf->rsrc3 = value;
90 conf->spi_ps_input_ena = value;
93 conf->spi_ps_input_addr = value;
98 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 256;
100 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 1024;
103 conf->spilled_sgprs = value;
106 conf->spilled_vgprs = value;
122 if (!conf->spi_ps_input_addr)
123 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
132 conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8);
143 conf->float_mode &= ~V_00B028_FP_32_DENORMS;
144 conf->float_mode |= V_00B028_FP_16_64_DENORMS;