Lines Matching refs:pOut
207 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const
240 pOut->dccRamSize = pIn->colorSurfSize >> 8;
241 pOut->dccRamBaseAlign = pIn->tileInfo.banks *
244 pOut->dccFastClearSize = dccFastClearSize;
245 pOut->dccRamSizeAligned = TRUE;
247 ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
249 if (0 == (pOut->dccRamSize & (pOut->dccRamBaseAlign - 1)))
251 pOut->subLvlCompressible = TRUE;
257 if (pOut->dccRamSize == pOut->dccFastClearSize)
259 pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
261 if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0)
263 pOut->dccRamSizeAligned = FALSE;
265 pOut->dccRamSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
266 pOut->subLvlCompressible = FALSE;
290 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut ///< [out] cmask address
313 pOut->addr = (metaNibbleAddress >> 1);
314 pOut->bitPosition = (metaNibbleAddress % 2) ? 4 : 0;
334 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut ///< [out] htile address
357 pOut->addr = (metaNibbleAddress >> 1);
358 pOut->bitPosition = 0;
696 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
702 pOut->macroModeIndex = TileIndexInvalid;
705 ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn, pOut);
708 (pOut->tcCompatible == TRUE) &&
709 (pOut->tileMode != pIn->tileMode) &&
712 pOut->tcCompatible = CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
715 if (pOut->macroModeIndex == TileIndexNoMacroIndex)
717 pOut->macroModeIndex = TileIndexInvalid;
723 pOut->stencilTileIdx = TileIndexInvalid;
725 if ((MinDepth2DThinIndex <= pOut->tileIndex) &&
726 (MaxDepth2DThinIndex >= pOut->tileIndex))
728 BOOL_32 depthStencil2DTileConfigMatch = DepthStencilTileCfgMatch(pIn, pOut);
731 (pOut->tcCompatible == TRUE))
733 pOut->macroModeIndex = TileIndexInvalid;
740 SiLib::HwlComputeSurfaceInfo(&localIn, pOut);
742 ADDR_ASSERT((MinDepth2DThinIndex <= pOut->tileIndex) && (MaxDepth2DThinIndex >= pOut->tileIndex));
744 depthStencil2DTileConfigMatch = DepthStencilTileCfgMatch(pIn, pOut);
750 pOut->macroModeIndex = TileIndexInvalid;
757 retCode = SiLib::HwlComputeSurfaceInfo(&localIn, pOut);
761 if (pOut->tileIndex == Depth1DThinIndex)
763 pOut->stencilTileIdx = Depth1DThinIndex;
781 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut ///< [out] output structure
792 // Use internal tile info if pOut does not have a valid pTileInfo
793 if (pOut->pTileInfo == NULL)
795 pOut->pTileInfo = &tileInfo;
832 macroModeIndex = HwlComputeMacroModeIndex(tileIndex, flags, bpp, numSamples, pOut->pTileInfo);
835 fmaskIn.pTileInfo = pOut->pTileInfo;
836 pOut->macroModeIndex = macroModeIndex;
837 pOut->tileIndex = tileIndex;
839 retCode = DispatchComputeFmaskInfo(&fmaskIn, pOut);
843 pOut->tileIndex =
844 HwlPostCheckTileIndex(pOut->pTileInfo, pIn->tileMode, ADDR_NON_DISPLAYABLE,
845 pOut->tileIndex);
849 if (pOut->pTileInfo == &tileInfo)
851 pOut->pTileInfo = NULL;
1257 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
1507 pOut->dccUnsupport = TRUE;
1515 index = pOut->tileIndex;
1516 macroModeIndex = pOut->macroModeIndex;
1519 pOut->tileType = inTileType;
1537 pOut->dccUnsupport = TRUE;
1546 // Copy to pOut->tileType/tileIndex/macroModeIndex
1547 pOut->tileIndex = index;
1548 pOut->tileType = m_tileTable[index].type; // Or inTileType, the samea
1549 pOut->macroModeIndex = macroModeIndex;
1553 pOut->tileIndex = TileIndexLinearGeneral;
1560 pOut->tileIndex = 8;
1566 flags.tcCompatible = CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
1569 pOut->tcCompatible = flags.tcCompatible;
2075 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Surface output
2086 (pOut->dccUnsupport == TRUE))
2088 pOut->pitchAlign = PowTwoAlign(pOut->pitchAlign, 256);
2090 pOut->dccUnsupport = FALSE;
2247 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
2266 m_macroTileTable[pOut->macroModeIndex].banks) &&
2268 m_macroTileTable[pOut->macroModeIndex].bankWidth) &&
2270 m_macroTileTable[pOut->macroModeIndex].bankHeight) &&
2272 m_macroTileTable[pOut->macroModeIndex].macroAspectRatio) &&
2274 m_macroTileTable[pOut->macroModeIndex].pipeConfig))
2276 if ((pOut->tcCompatible == FALSE) ||
2280 pOut->stencilTileIdx = stencilTileIndex;
2309 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in] output surf info
2320 INT_32 tileIndex = pOut->tileIndex;