Lines Matching refs:__u64
150 __u64 bo_size;
152 __u64 alignment;
154 __u64 domains;
156 __u64 domain_flags;
187 __u64 bo_info_ptr;
273 __u64 flags;
303 __u64 flags;
339 __u64 addr;
340 __u64 size;
382 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
384 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
397 __u64 flags;
399 __u64 tiling_info;
413 __u64 addr_ptr;
427 __u64 timeout;
447 __u64 handle;
449 __u64 timeout;
458 __u64 status;
471 __u64 seq_no;
476 __u64 fences;
479 __u64 timeout_ns;
502 __u64 value;
548 __u64 va_address;
550 __u64 offset_in_bo;
552 __u64 map_size;
581 __u64 chunk_data;
591 /** this points to __u64 * which point to cs chunks */
592 __u64 chunks;
596 __u64 handle;
637 __u64 va_start;
653 __u64 handle;
668 __u64 point;
871 __u64 return_pointer;
939 __u64 vram_size;
940 __u64 vram_cpu_accessible_size;
941 __u64 gtt_size;
946 __u64 total_heap_size;
949 __u64 usable_heap_size;
957 __u64 heap_usage;
963 __u64 max_allocation;
1011 __u64 max_engine_clock;
1012 __u64 max_memory_clock;
1023 __u64 ids_flags;
1025 __u64 virtual_address_offset;
1027 __u64 virtual_address_max;
1044 __u64 prim_buf_gpu_addr;
1046 __u64 pos_buf_gpu_addr;
1048 __u64 cntl_sb_buf_gpu_addr;
1050 __u64 param_buf_gpu_addr;
1073 __u64 high_va_offset;
1075 __u64 high_va_max;
1079 __u64 tcc_disabled_mask;
1087 __u64 capabilities_flags;