Lines Matching refs:ii
135 #define DECLARE_VAR(reg, ii) __m128i reg;
136 #define LOAD_data( reg, ii) reg = data[ii];
137 #define STORE_data( reg, ii) data[ii] = reg;
139 #define XOR_data_M1(reg, ii) MM_XOR (reg, data[ii- 1])
142 #define AVX_DECLARE_VAR(reg, ii) __m256i reg;
143 #define AVX_LOAD_data( reg, ii) reg = ((const __m256i *)(const void *)data)[ii];
144 #define AVX_STORE_data( reg, ii) ((__m256i *)(void *)data)[ii] = reg;
145 #define AVX_XOR_data_M1(reg, ii) AVX_XOR (reg, (((const __m256i *)(const void *)(data - 1))[ii]))
149 #define AES_DEC( reg, ii) MM_OP_key (_mm_aesdec_si128, reg)
150 #define AES_DEC_LAST( reg, ii) MM_OP_key (_mm_aesdeclast_si128, reg)
151 #define AES_ENC( reg, ii) MM_OP_key (_mm_aesenc_si128, reg)
152 #define AES_ENC_LAST( reg, ii) MM_OP_key (_mm_aesenclast_si128, reg)
153 #define AES_XOR( reg, ii) MM_OP_key (_mm_xor_si128, reg)
156 #define AVX_AES_DEC( reg, ii) MM_OP_key (_mm256_aesdec_epi128, reg)
157 #define AVX_AES_DEC_LAST( reg, ii) MM_OP_key (_mm256_aesdeclast_epi128, reg)
158 #define AVX_AES_ENC( reg, ii) MM_OP_key (_mm256_aesenc_epi128, reg)
159 #define AVX_AES_ENC_LAST( reg, ii) MM_OP_key (_mm256_aesenclast_epi128, reg)
160 #define AVX_AES_XOR( reg, ii) MM_OP_key (_mm256_xor_si256, reg)
162 #define CTR_START(reg, ii) MM_OP (_mm_add_epi64, ctr, one) reg = ctr;
163 #define CTR_END( reg, ii) MM_XOR (data[ii], reg)
165 #define AVX_CTR_START(reg, ii) MM_OP (_mm256_add_epi64, ctr2, two) reg = _mm256_xor_si256(ctr2, key);
166 #define AVX_CTR_END( reg, ii) AVX_XOR (((__m256i *)(void *)data)[ii], reg)
199 UInt32 ii; \
201 for (ii = 0; ii < numRounds; ii++) \
202 keys[ii] = _mm256_broadcastsi128_si256(p[ii]); \
684 #define DECLARE_VAR(reg, ii) v128 reg;
685 #define LOAD_data( reg, ii) reg = data[ii];
686 #define STORE_data( reg, ii) data[ii] = reg;
688 #define XOR_data_M1(reg, ii) MM_XOR (reg, data[ii- 1])
696 #define AES_XOR( reg, ii) MM_OP_key (veorq_u8, reg)
697 #define AES_D( reg, ii) MM_OP_key (vaesdq_u8, reg)
698 #define AES_E( reg, ii) MM_OP_key (vaeseq_u8, reg)
700 #define AES_D_IMC( reg, ii) AES_D (reg, ii) reg = vaesimcq_u8(reg);
701 #define AES_E_MC( reg, ii) AES_E (reg, ii) reg = vaesmcq_u8(reg);
703 #define CTR_START(reg, ii) MM_OP (vaddq_u64, ctr, one) reg = vreinterpretq_u8_u64(ctr);
704 #define CTR_END( reg, ii) MM_XOR (data[ii], reg)