Lines Matching refs:output_insn
256 static void FORMAT_ATTR(2) output_insn(struct bb_state *state, const char *fmt, ...)
268 #define output_insn(state, fmt, arg...) \
269 output_insn(state, fmt "\t\t# %s" , ## arg , __FUNCTION__)
376 output_insn(state, "movl %s,%s", hardreg->name, show_memop(storage));
555 output_insn(state, "%s %s", opcodes[opcode], reg->name);
596 output_insn(state, "movl $%lld,%s", pseudo->value, hardreg->name);
602 output_insn(state, "movl $<%s>,%s", show_pseudo(pseudo), hardreg->name);
616 output_insn(state, "leal %s,%s", show_memop(src->storage), hardreg->name);
624 output_insn(state, "movl $<%s>,%s", show_pseudo(def->target), hardreg->name);
632 output_insn(state, "mov.%d %s,%s", 32, show_memop(src->storage), hardreg->name);
635 output_insn(state, "reload %s from %s", hardreg->name, show_pseudo(pseudo));
654 output_insn(state, "movl %s,%s", src->name, dst->name);
681 output_insn(state, "movl %s,%s", src->name, reg->name);
816 output_insn(state, "lea %s,%s", show_op(state, op), reg->name);
895 output_insn(state, "%s.%d %s,%s", op, insn->size, show_op(state, src2), dst->name);
982 output_insn(state, "mov.%d %s,%s", insn->size, reg_or_imm(state, insn->target), address(state, insn));
992 output_insn(state, "mov.%d %s,%s", insn->size, input, dst->name);
1044 output_insn(state, "sext.%d.%d %s", old, new, dst->name);
1049 output_insn(state, "andl.%d $%#llx,%s", insn->size, mask, dst->name);
1080 output_insn(state, "testl %s,%s", reg->name, reg->name);
1087 output_insn(state, "j%s .L%p", cond, target);
1090 output_insn(state, "jmp .L%p", target);
1099 output_insn(state, "switch on %s", reg->name);
1100 output_insn(state, "unimplemented: %s", show_instruction(insn));
1109 output_insn(state, "movl %s,%s", reg->name, wants->name);
1111 output_insn(state, "ret");
1123 output_insn(state, "pushl %s", generic(state, arg));
1129 output_insn(state, "call %s", show_pseudo(insn->func));
1131 output_insn(state, "addl $%d,%%esp", offset);
1150 output_insn(state, "testl %s,%s", reg->name, reg->name);
1154 output_insn(state, "sel%s %s,%s", cond, src2->name, dst->name);
1283 output_insn(state, "# asm input \"%s\": %s : %s", constraint, show_pseudo(pseudo), string);
1318 output_insn(state, "# asm output \"%s\": %s : %s", constraint, show_pseudo(pseudo), string);
1338 output_insn(state, "%s", str);
1357 output_insn(state, "cmp.%d %s,%s", insn->size, src2, src->name);
1457 output_insn(state, "unimplemented: %s", show_instruction(insn));
1476 output_insn(state, "movl %s,%s", reg->name, out->name);
1491 output_insn(state, "movl %s,%s", reg->name, out->name);
1502 output_insn(state, "movl %s,%s", reg->name, show_memop(storage));
1515 output_insn(state, "movl %s,%s", show_pseudo(src), show_memop(storage));
1519 output_insn(state, "movl %s,%s", show_pseudo(src), out->name);
1570 output_insn(state, "movl %s,%s", show_memop(in->storage), hardregs[out->regno].name);
1577 output_insn(state, "movl %s,%s", show_memop(in->storage), show_memop(out));
1629 output_insn(state, "movl %s,%s", reg->name, show_memop(out));
1635 output_insn(state, "movl %s,%s", reg->name, dst->name);