Lines Matching refs:pre
151 uint8_t pre[128];
170 pre[0] = LWSSS_SER_RXPRE_RX_PAYLOAD;
171 lws_ser_wu16be(&pre[1], (uint16_t)(len + (size_t)est - 3));
172 lws_ser_wu32be(&pre[3], (uint32_t)flags);
173 lws_ser_wu32be(&pre[7], 0); /* write will compute latency here... */
174 lws_ser_wu64be(&pre[11], (uint64_t)us); /* ... and set this to the write time */
182 pre[19] = (uint8_t)l;
183 memcpy(&pre[20], rsp, (unsigned int)l);
186 if (lws_dsh_alloc_tail(dsh, KIND_SS_TO_P, pre, (unsigned int)est, buf, len)) {
263 uint8_t pre[12];
272 pre[0] = LWSSS_SER_RXPRE_CONNSTATE;
273 pre[1] = 0;
276 pre[2] = 8;
277 lws_ser_wu32be(&pre[3], state);
280 pre[2] = 5;
281 pre[3] = (uint8_t)state;
284 lws_ser_wu32be(&pre[n], ack);
286 if (lws_dsh_alloc_tail(dsh, KIND_SS_TO_P, pre, (unsigned int)n + 4, NULL, 0) ||
304 uint8_t pre[7];
308 pre[0] = LWSSS_SER_RXPRE_TXCR_UPDATE;
309 pre[1] = 0;
310 pre[2] = 4;
311 lws_ser_wu32be(&pre[3], (uint32_t)txcr);
313 if (lws_dsh_alloc_tail(dsh, KIND_SS_TO_P, pre, 7, NULL, 0)) {
368 uint8_t pre[23];
728 p = pre;
729 pre[0] = LWSSS_SER_TXPRE_TX_PAYLOAD;
741 lws_dsh_alloc_tail(dsh, KIND_C_TO_P, pre,