Lines Matching refs:ptr
107 static uint32_t *ptr;
222 ptr[256] = 0x1;
267 ptr = ib_result_cpu;
269 ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5);
270 ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
273 ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc;
274 ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
275 ptr[4] = 0x00000000; /* reference value */
276 ptr[5] = 0xffffffff; /* and mask */
277 ptr[6] = 0x00000004; /* poll interval */
280 ptr[i] = 0xffff1000;
283 ptr[256] = 0x0; /* the memory we wait on to change */
364 ptr = ib_result_cpu;
367 ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
371 ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffffffc;
372 ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
373 ptr[i++] = 0x00000000; /* reference value */
374 ptr[i++] = 0xffffffff; /* and mask */
375 ptr[i++] = 4 | /* poll interval */
379 ptr[i] = 0;
381 ptr[256] = 0x0; /* the memory we wait on to change */
452 ptr = ib_result_cpu;
455 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
456 ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM;
457 ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0;
458 ptr[i++] = 0;
459 ptr[i++] = 0xdeadbeef;
462 ptr[i] = 0xffff1000;