Lines Matching refs:ibs_request
243 struct amdgpu_cs_request ibs_request;
291 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
292 ibs_request.ip_type = ip_type;
293 ibs_request.ring = 0;
294 ibs_request.number_of_ibs = 1;
295 ibs_request.ibs = &ib_info;
296 ibs_request.resources = bo_list;
297 ibs_request.fence_info.handle = NULL;
299 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
309 fence_status.fence = ibs_request.seq_no;
334 struct amdgpu_cs_request ibs_request;
387 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
388 ibs_request.ip_type = AMDGPU_HW_IP_DMA;
389 ibs_request.ring = ring_id;
390 ibs_request.number_of_ibs = 1;
391 ibs_request.ibs = &ib_info;
392 ibs_request.resources = bo_list;
393 ibs_request.fence_info.handle = NULL;
396 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
406 fence_status.fence = ibs_request.seq_no;
431 struct amdgpu_cs_request ibs_request;
468 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
469 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
470 ibs_request.ring = 0;
471 ibs_request.number_of_ibs = 1;
472 ibs_request.ibs = &ib_info;
473 ibs_request.resources = bo_list;
474 ibs_request.fence_info.handle = NULL;
476 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
485 fence_status.fence = ibs_request.seq_no;