Lines Matching refs:ibs_request
75 struct amdgpu_cs_request *ibs_request);
852 struct amdgpu_cs_request ibs_request = {0};
901 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
902 ibs_request.number_of_ibs = 2;
903 ibs_request.ibs = ib_info;
904 ibs_request.resources = bo_list;
905 ibs_request.fence_info.handle = NULL;
907 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
914 fence_status.fence = ibs_request.seq_no;
943 struct amdgpu_cs_request ibs_request = {0};
985 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
986 ibs_request.number_of_ibs = 2;
987 ibs_request.ibs = ib_info;
988 ibs_request.resources = bo_list;
989 ibs_request.fence_info.handle = NULL;
991 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
998 fence_status.fence = ibs_request.seq_no;
1040 struct amdgpu_cs_request *ibs_request;
1054 ibs_request = calloc(1, sizeof(*ibs_request));
1055 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1147 ib_info, ibs_request);
1171 free(ibs_request);
1202 struct amdgpu_cs_request ibs_request[2] = {0};
1251 ibs_request[0].ip_type = AMDGPU_HW_IP_DMA;
1252 ibs_request[0].number_of_ibs = 1;
1253 ibs_request[0].ibs = &ib_info[0];
1254 ibs_request[0].resources = bo_list[0];
1255 ibs_request[0].fence_info.handle = NULL;
1256 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
1268 ibs_request[1].ip_type = gc_ip_type;
1269 ibs_request[1].number_of_ibs = 1;
1270 ibs_request[1].ibs = &ib_info[1];
1271 ibs_request[1].resources = bo_list[1];
1272 ibs_request[1].fence_info.handle = NULL;
1274 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[1], 1);
1280 fence_status.fence = ibs_request[1].seq_no;
1292 ibs_request[0].ip_type = gc_ip_type;
1293 ibs_request[0].number_of_ibs = 1;
1294 ibs_request[0].ibs = &ib_info[0];
1295 ibs_request[0].resources = bo_list[0];
1296 ibs_request[0].fence_info.handle = NULL;
1297 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
1309 ibs_request[1].ip_type = gc_ip_type;
1310 ibs_request[1].number_of_ibs = 1;
1311 ibs_request[1].ibs = &ib_info[1];
1312 ibs_request[1].resources = bo_list[1];
1313 ibs_request[1].fence_info.handle = NULL;
1314 r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1);
1321 fence_status.fence = ibs_request[1].seq_no;
1349 struct amdgpu_cs_request ibs_request;
1384 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
1385 ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE;
1386 ibs_request.ring = instance;
1387 ibs_request.number_of_ibs = 1;
1388 ibs_request.ibs = &ib_info;
1389 ibs_request.resources = bo_list;
1390 ibs_request.fence_info.handle = NULL;
1393 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
1400 fence_status.fence = ibs_request.seq_no;
1448 * pm4_src, resources, ib_info, and ibs_request
1449 * submit command stream described in ibs_request and wait for this IB accomplished
1458 struct amdgpu_cs_request *ibs_request,
1475 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1494 ibs_request->ip_type = ip_type;
1495 ibs_request->ring = instance;
1496 ibs_request->number_of_ibs = 1;
1497 ibs_request->ibs = ib_info;
1498 ibs_request->fence_info.handle = NULL;
1504 NULL, &ibs_request->resources);
1507 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1510 r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1);
1513 r = amdgpu_bo_list_destroy(ibs_request->resources);
1518 fence_status.ring = ibs_request->ring;
1520 fence_status.fence = ibs_request->seq_no;
1540 struct amdgpu_cs_request *ibs_request)
1545 ibs_request, false);
1560 struct amdgpu_cs_request *ibs_request;
1575 ibs_request = calloc(1, sizeof(*ibs_request));
1576 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1639 ibs_request, secure);
1669 ibs_request, true);
1693 ibs_request, true);
1726 ibs_request, true);
1739 free(ibs_request);
1769 struct amdgpu_cs_request *ibs_request;
1783 ibs_request = calloc(1, sizeof(*ibs_request));
1784 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1863 ib_info, ibs_request);
1879 free(ibs_request);
1902 struct amdgpu_cs_request *ibs_request;
1916 ibs_request = calloc(1, sizeof(*ibs_request));
1917 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
2017 ib_info, ibs_request);
2037 free(ibs_request);
2064 struct amdgpu_cs_request ibs_request[2] = {0};
2115 ibs_request[i].ip_type = AMDGPU_HW_IP_GFX;
2116 ibs_request[i].number_of_ibs = 2;
2117 ibs_request[i].ibs = ib_info;
2118 ibs_request[i].resources = bo_list;
2119 ibs_request[i].fence_info.handle = NULL;
2122 r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num);
2129 fence_status[i].fence = ibs_request[i].seq_no;
2169 struct amdgpu_cs_request *ibs_request;
2179 ibs_request = calloc(1, sizeof(*ibs_request));
2180 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
2231 ib_info, ibs_request);
2236 free(ibs_request);
2260 struct amdgpu_cs_request ibs_request;
2381 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
2382 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
2383 ibs_request.ring = 0;
2384 ibs_request.number_of_ibs = 1;
2385 ibs_request.ibs = &ib_info;
2386 ibs_request.resources = bo_list;
2387 ibs_request.fence_info.handle = NULL;
2389 r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1);
2391 seq_no = ibs_request.seq_no;
2410 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
2411 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
2412 ibs_request.ring = 0;
2413 ibs_request.number_of_ibs = 1;
2414 ibs_request.ibs = &ib_info;
2415 ibs_request.resources = bo_list;
2416 ibs_request.fence_info.handle = NULL;
2418 ibs_request.number_of_dependencies = 1;
2420 ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies));
2421 ibs_request.dependencies[0].context = context_handle[1];
2422 ibs_request.dependencies[0].ip_instance = 0;
2423 ibs_request.dependencies[0].ring = 0;
2424 ibs_request.dependencies[0].fence = seq_no;
2427 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1);
2436 fence_status.fence = ibs_request.seq_no;
2457 free(ibs_request.dependencies);
2651 struct amdgpu_cs_request ibs_request = {0};
2735 ibs_request.ip_type = ip_type;
2736 ibs_request.ring = ring;
2737 ibs_request.resources = bo_list;
2738 ibs_request.number_of_ibs = 1;
2739 ibs_request.ibs = &ib_info;
2740 ibs_request.fence_info.handle = NULL;
2743 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
2753 fence_status.fence = ibs_request.seq_no;
2799 struct amdgpu_cs_request ibs_request = {0};
2897 ibs_request.ip_type = ip_type;
2898 ibs_request.ring = ring;
2899 ibs_request.resources = bo_list;
2900 ibs_request.number_of_ibs = 1;
2901 ibs_request.ibs = &ib_info;
2902 ibs_request.fence_info.handle = NULL;
2903 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
2910 fence_status.fence = ibs_request.seq_no;
3036 struct amdgpu_cs_request ibs_request = {0};
3136 ibs_request.ip_type = ip_type;
3137 ibs_request.ring = ring;
3138 ibs_request.resources = bo_list;
3139 ibs_request.number_of_ibs = 1;
3140 ibs_request.ibs = &ib_info;
3141 ibs_request.fence_info.handle = NULL;
3142 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
3149 fence_status.fence = ibs_request.seq_no;
3735 struct amdgpu_cs_request ibs_request = {0};
3790 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
3791 ibs_request.ring = ring_id;
3792 ibs_request.resources = bo_list;
3793 ibs_request.number_of_ibs = 1;
3794 ibs_request.ibs = &ib_info;
3795 ibs_request.fence_info.handle = NULL;
3798 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
3808 fence_status.fence = ibs_request.seq_no;
3892 struct amdgpu_cs_request ibs_request = {0};
3979 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
3980 ibs_request.ring = ring;
3981 ibs_request.resources = bo_list;
3982 ibs_request.number_of_ibs = 1;
3983 ibs_request.ibs = &ib_info;
3984 ibs_request.fence_info.handle = NULL;
3985 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
3992 fence_status.fence = ibs_request.seq_no;
4115 struct amdgpu_cs_request ibs_request = {0};
4223 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
4224 ibs_request.ring = ring;
4225 ibs_request.resources = bo_list;
4226 ibs_request.number_of_ibs = 1;
4227 ibs_request.ibs = &ib_info;
4228 ibs_request.fence_info.handle = NULL;
4229 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
4236 fence_status.fence = ibs_request.seq_no;