xref: /third_party/libdrm/tests/amdgpu/basic_tests.c

2644 	uint32_t *ptr_cmd;
2662 					&bo_cmd, (void **)&ptr_cmd,
2665 	memset(ptr_cmd, 0, bo_cmd_size);
2684 	i += amdgpu_dispatch_init(ptr_cmd + i, ip_type, version);
2687 	i += amdgpu_dispatch_write_cumask(ptr_cmd + i, version);
2690 	i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader, version);
2694 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
2695 	ptr_cmd[i++] = 0x240;
2696 	ptr_cmd[i++] = mc_address_dst;
2697 	ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
2698 	ptr_cmd[i++] = 0x400;
2700 		ptr_cmd[i++] = 0x74fac;
2702 		ptr_cmd[i++] = 0x1104bfac;
2705 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
2706 	ptr_cmd[i++] = 0x244;
2707 	ptr_cmd[i++] = 0x22222222;
2708 	ptr_cmd[i++] = 0x22222222;
2709 	ptr_cmd[i++] = 0x22222222;
2710 	ptr_cmd[i++] = 0x22222222;
2713 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
2714 	ptr_cmd[i++] = 0x215;
2715 	ptr_cmd[i++] = 0;
2718 	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
2719 	ptr_cmd[i++] = 0x10;
2720 	ptr_cmd[i++] = 1;
2721 	ptr_cmd[i++] = 1;
2722 	ptr_cmd[i++] = 1;
2725 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
2792 	uint32_t *ptr_cmd;
2811 				    &bo_cmd, (void **)&ptr_cmd,
2814 	memset(ptr_cmd, 0, bo_cmd_size);
2842 	i += amdgpu_dispatch_init(ptr_cmd + i, ip_type, version);
2845 	i += amdgpu_dispatch_write_cumask(ptr_cmd + i, version);
2848 	i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader, version);
2852 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
2853 	ptr_cmd[i++] = 0x240;
2854 	ptr_cmd[i++] = mc_address_src;
2855 	ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000;
2856 	ptr_cmd[i++] = 0x400;
2858 		ptr_cmd[i++] = 0x74fac;
2860 		ptr_cmd[i++] = 0x1104bfac;
2863 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
2864 	ptr_cmd[i++] = 0x244;
2865 	ptr_cmd[i++] = mc_address_dst;
2866 	ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
2867 	ptr_cmd[i++] = 0x400;
2869 		ptr_cmd[i++] = 0x74fac;
2871 		ptr_cmd[i++] = 0x1104bfac;
2874 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
2875 	ptr_cmd[i++] = 0x215;
2876 	ptr_cmd[i++] = 0;
2879 	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
2880 	ptr_cmd[i++] = 0x10;
2881 	ptr_cmd[i++] = 1;
2882 	ptr_cmd[i++] = 1;
2883 	ptr_cmd[i++] = 1;
2886 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
3029 	uint32_t *ptr_cmd;
3051 				    &bo_cmd, (void **)&ptr_cmd,
3054 	memset(ptr_cmd, 0, bo_cmd_size);
3081 	i += amdgpu_dispatch_init(ptr_cmd + i, ip_type, version);
3084 	i += amdgpu_dispatch_write_cumask(ptr_cmd + i, version);
3087 	i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader, version);
3091 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
3092 	ptr_cmd[i++] = 0x240;
3093 	ptr_cmd[i++] = mc_address_src;
3094 	ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000;
3095 	ptr_cmd[i++] = 0x400000;
3097 		ptr_cmd[i++] = 0x74fac;
3099 		ptr_cmd[i++] = 0x1104bfac;
3102 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
3103 	ptr_cmd[i++] = 0x244;
3104 	ptr_cmd[i++] = mc_address_dst;
3105 	ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
3106 	ptr_cmd[i++] = 0x400000;
3108 		ptr_cmd[i++] = 0x74fac;
3110 		ptr_cmd[i++] = 0x1104bfac;
3113 	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
3114 	ptr_cmd[i++] = 0x215;
3115 	ptr_cmd[i++] = 0;
3118 	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
3119 	ptr_cmd[i++] = 0x10000;
3120 	ptr_cmd[i++] = 1;
3121 	ptr_cmd[i++] = 1;
3122 	ptr_cmd[i++] = 1;
3125 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
3729 	uint32_t *ptr_cmd;
3746 					&bo_cmd, (void **)&ptr_cmd,
3749 	memset(ptr_cmd, 0, bo_cmd_size);
3758 	i += amdgpu_draw_init(ptr_cmd + i, version);
3760 	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, version, 0);
3762 	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, version, 0);
3764 	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs,
3767 	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps, version);
3769 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
3770 	ptr_cmd[i++] = 0xc;
3771 	ptr_cmd[i++] = 0x33333333;
3772 	ptr_cmd[i++] = 0x33333333;
3773 	ptr_cmd[i++] = 0x33333333;
3774 	ptr_cmd[i++] = 0x33333333;
3776 	i += amdgpu_draw_draw(ptr_cmd + i, version);
3779 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
3886 	uint32_t *ptr_cmd;
3904 				    &bo_cmd, (void **)&ptr_cmd,
3907 	memset(ptr_cmd, 0, bo_cmd_size);
3924 	i += amdgpu_draw_init(ptr_cmd + i, version);
3926 	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, version, 0);
3928 	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, version, 0);
3930 	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs,
3933 	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps, version);
3935 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8);
3937 		ptr_cmd[i++] = 0xc;
3938 		ptr_cmd[i++] = mc_address_src >> 8;
3939 		ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
3940 		ptr_cmd[i++] = 0x7c01f;
3941 		ptr_cmd[i++] = 0x90500fac;
3942 		ptr_cmd[i++] = 0x3e000;
3945 		ptr_cmd[i++] = 0xc;
3946 		ptr_cmd[i++] = mc_address_src >> 8;
3947 		ptr_cmd[i++] = mc_address_src >> 40 | 0xc4b00000;
3948 		ptr_cmd[i++] = 0x8007c007;
3949 		ptr_cmd[i++] = 0x90500fac;
3951 		ptr_cmd[i++] = 0x400;
3955 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
3956 	ptr_cmd[i++] = 0x14;
3957 	ptr_cmd[i++] = 0x92;
3960 	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3961 	ptr_cmd[i++] = 0x191;
3962 	ptr_cmd[i++] = 0;
3964 	i += amdgpu_draw_draw(ptr_cmd + i, version);
3967 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
4104 	uint32_t *ptr_cmd;
4129 				    &bo_cmd, (void **)&ptr_cmd,
4132 	memset(ptr_cmd, 0, bo_cmd_size);
4169 	i += amdgpu_draw_init(ptr_cmd + i, version);
4171 	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, version, 1);
4173 	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, version, 1);
4175 	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX,
4178 	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps, version);
4180 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8);
4183 		ptr_cmd[i++] = 0xc;
4184 		ptr_cmd[i++] = mc_address_src >> 8;
4185 		ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
4186 		ptr_cmd[i++] = 0x1ffcfff;
4187 		ptr_cmd[i++] = 0x90500fac;
4188 		ptr_cmd[i++] = 0x1ffe000;
4191 		ptr_cmd[i++] = 0xc;
4192 		ptr_cmd[i++] = mc_address_src >> 8;
4193 		ptr_cmd[i++] = mc_address_src >> 40 | 0xc4b00000;
4194 		ptr_cmd[i++] = 0x81ffc1ff;
4195 		ptr_cmd[i++] = 0x90500fac;
4199 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
4200 	ptr_cmd[i++] = 0x14;
4201 	ptr_cmd[i++] = 0x92;
4204 	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
4205 	ptr_cmd[i++] = 0x191;
4206 	ptr_cmd[i++] = 0;
4208 	i += amdgpu_draw_draw(ptr_cmd + i, version);
4211 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */

Indexes created Thu Nov 07 10:32:03 CST 2024