Lines Matching defs:ptr
855 uint32_t *ptr;
883 ptr = ib_result_ce_cpu;
885 ptr[i++] = 0xc0008900;
886 ptr[i++] = 0;
888 ptr[i++] = 0xc0008400;
889 ptr[i++] = 1;
895 ptr = ib_result_cpu;
896 ptr[0] = 0xc0008600;
897 ptr[1] = 0x00000001;
946 uint32_t *ptr;
968 ptr = ib_result_cpu;
970 ptr[i++] = 0xc0008900;
971 ptr[i++] = 0;
973 ptr[i++] = 0xc0008400;
974 ptr[i++] = 1;
979 ptr = (uint32_t *)ib_result_cpu + 4;
980 ptr[0] = 0xc0008600;
981 ptr[1] = 0x00000001;
1205 uint32_t *ptr;
1246 ptr = ib_result_cpu[0];
1247 ptr[0] = sdma_nop;
1263 ptr = ib_result_cpu[1];
1264 ptr[0] = gfx_nop;
1287 ptr = ib_result_cpu[0];
1288 ptr[0] = gfx_nop;
1304 ptr = ib_result_cpu[1];
1305 ptr[0] = gfx_nop;
1352 uint32_t *ptr;
1376 ptr = ib_result_cpu;
1377 memset(ptr, 0, 16);
1378 ptr[0]=PACKET3(PACKET3_NOP, 14);
2067 uint32_t *ptr;
2096 ptr = ib_result_ce_cpu;
2098 ptr[i++] = 0xc0008900;
2099 ptr[i++] = 0;
2101 ptr[i++] = 0xc0008400;
2102 ptr[i++] = 1;
2108 ptr = ib_result_cpu;
2109 ptr[0] = 0xc0008600;
2110 ptr[1] = 0x00000001;
2163 void *ptr = NULL;
2185 posix_memalign(&ptr, sysconf(_SC_PAGE_SIZE), BUFFER_SIZE);
2186 CU_ASSERT_NOT_EQUAL(ptr, NULL);
2187 memset(ptr, 0, BUFFER_SIZE);
2190 ptr, BUFFER_SIZE, &buf_handle);
2234 CU_ASSERT_EQUAL(((int*)ptr)[i++], 0xdeadbeaf);
2246 free(ptr);
2267 static uint32_t *ptr;
2285 ptr = ib_result_cpu;
2288 memcpy(ptr + CODE_OFFSET , shader_bin, sizeof(shader_bin));
2291 ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
2292 ptr[i++] = 0x80000000;
2293 ptr[i++] = 0x80000000;
2295 ptr[i++] = PACKET3(PKT3_CLEAR_STATE, 0);
2296 ptr[i++] = 0x80000000;
2300 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
2301 ptr[i++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
2302 ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 8;
2303 ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 40;
2306 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
2307 ptr[i++] = mmCOMPUTE_PGM_RSRC1 - PACKET3_SET_SH_REG_START;
2321 ptr[i++] = 0x002c0040;
2338 ptr[i++] = 0x00000010;
2346 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
2347 ptr[i++] = mmCOMPUTE_TMPRING_SIZE - PACKET3_SET_SH_REG_START;
2348 ptr[i++] = 0x00000100;
2350 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
2351 ptr[i++] = mmCOMPUTE_USER_DATA_0 - PACKET3_SET_SH_REG_START;
2352 ptr[i++] = 0xffffffff & (ib_result_mc_address + DATA_OFFSET * 4);
2353 ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
2355 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
2356 ptr[i++] = mmCOMPUTE_RESOURCE_LIMITS - PACKET3_SET_SH_REG_START;
2357 ptr[i++] = 0;
2359 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
2360 ptr[i++] = mmCOMPUTE_NUM_THREAD_X - PACKET3_SET_SH_REG_START;
2361 ptr[i++] = 1;
2362 ptr[i++] = 1;
2363 ptr[i++] = 1;
2367 ptr[i++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
2368 ptr[i++] = 1;
2369 ptr[i++] = 1;
2370 ptr[i++] = 1;
2371 ptr[i++] = 0x00000045; /* DISPATCH DIRECT field */
2375 ptr[i++] = 0xffff1000; /* type3 nop packet */
2397 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
2398 ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
2399 ptr[i++] = 0xfffffffc & (ib_result_mc_address + DATA_OFFSET * 4);
2400 ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
2401 ptr[i++] = 99;
2404 ptr[i++] = 0xffff1000; /* type3 nop packet */
2443 CU_ASSERT_EQUAL(ptr[DATA_OFFSET], 99);
2460 static int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, int family)
2480 memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t));
2483 memcpy(ptr + shader->header_length + shader->body_length * i,
2487 memcpy(ptr + shader->header_length + shader->body_length * loop,
2494 static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
2529 memcpy(ptr, shader, shader_size);
2533 static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type, uint32_t version)
2539 ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
2540 ptr[i++] = 0x80000000;
2541 ptr[i++] = 0x80000000;
2546 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
2547 ptr[i++] = 0x204;
2551 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
2552 ptr[i++] = 0x218;
2553 ptr[i++] = 0;
2558 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
2559 ptr[i++] = 0x22a;
2560 ptr[i++] = 0;
2562 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 6);
2563 ptr[i++] = 0x222;
2566 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2567 ptr[i++] = 0x7b;
2568 ptr[i++] = 0x20;
2573 static int amdgpu_dispatch_write_cumask(uint32_t *ptr, uint32_t version)
2580 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
2581 ptr[i++] = 0x216;
2582 ptr[i++] = 0xffffffff;
2583 ptr[i++] = 0xffffffff;
2585 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
2586 ptr[i++] = 0x219;
2587 ptr[i++] = 0xffffffff;
2588 ptr[i++] = 0xffffffff;
2591 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2);
2592 ptr[i++] = 0x30000216;
2593 ptr[i++] = 0xffffffff;
2594 ptr[i++] = 0xffffffff;
2596 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2);
2597 ptr[i++] = 0x30000219;
2598 ptr[i++] = 0xffffffff;
2599 ptr[i++] = 0xffffffff;
2605 static int amdgpu_dispatch_write2hw(uint32_t *ptr, uint64_t shader_addr, uint32_t version)
2613 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
2614 ptr[i++] = 0x20c;
2615 ptr[i++] = (shader_addr >> 8);
2616 ptr[i++] = (shader_addr >> 40);
2619 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
2621 ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][0] - 0x2c00;
2622 ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][1];
2627 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
2628 ptr[i++] = 0x228;
2629 ptr[i++] = 0;
3202 static int amdgpu_draw_load_ps_shader_hang_slow(uint32_t *ptr, int family)
3217 memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t));
3220 memcpy(ptr + shader->header_length + shader->body_length * i,
3224 memcpy(ptr + shader->header_length + shader->body_length * loop,
3231 static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type, uint32_t version)
3276 memcpy(ptr, shader, shader_size);
3286 memcpy(ptr + mem_offset, shader, shader_size);
3293 memcpy(ptr + mem_offset,
3302 static int amdgpu_draw_load_vs_shader(uint8_t *ptr, uint32_t version)
3315 memcpy(ptr, shader, shader_size);
3320 static int amdgpu_draw_init(uint32_t *ptr, uint32_t version)
3327 ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
3328 ptr[i++] = 0x80000000;
3329 ptr[i++] = 0x80000000;
3339 memcpy(ptr + i, preamblecache_ptr, preamblecache_size);
3343 static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
3368 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15);
3369 ptr[i++] = 0x318;
3370 ptr[i++] = dst_addr >> 8;
3371 ptr[i++] = dst_addr >> 40;
3372 ptr[i++] = hang_slow ? 0x3ffc7ff : 0x7c01f;
3373 ptr[i++] = 0;
3374 ptr[i++] = 0x50438;
3375 ptr[i++] = 0x10140000;
3379 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3380 ptr[i++] = 0x1e8;
3381 ptr[i++] = hang_slow ? 0xfff : 0x1f;
3397 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 14);
3398 ptr[i++] = 0x318;
3399 ptr[i++] = dst_addr >> 8;
3401 ptr[i++] = 0x50438;
3405 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3406 ptr[i++] = 0x390;
3407 ptr[i++] = dst_addr >> 40;
3410 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3411 ptr[i++] = 0x398;
3412 ptr[i++] = 0;
3415 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3416 ptr[i++] = 0x3a0;
3417 ptr[i++] = 0;
3420 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3421 ptr[i++] = 0x3a8;
3422 ptr[i++] = 0;
3425 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3426 ptr[i++] = 0x3b0;
3427 ptr[i++] = hang_slow ? 0x3ffc7ff : 0x7c01f;
3430 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3431 ptr[i++] = 0x3b8;
3432 ptr[i++] = 0x9014000;
3436 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3437 ptr[i++] = 0x32b;
3438 ptr[i++] = 0;
3441 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3442 ptr[i++] = 0x33a;
3443 ptr[i++] = 0;
3446 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3447 ptr[i++] = 0x1c5;
3448 ptr[i++] = 9;
3453 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
3454 ptr[i++] = 0xe;
3458 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
3459 ptr[i++] = 0x10;
3466 static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr,
3475 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3476 ptr[i++] = 0xd7;
3477 ptr[i++] = 0;
3479 ptr[i++] = 0xffff1000;
3480 ptr[i++] = 0xc0021000;
3482 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3483 ptr[i++] = 0xd7;
3485 ptr[i++] = 1;
3487 ptr[i++] = 0;
3490 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
3491 ptr[i++] = 0x2fe;
3495 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
3496 ptr[i++] = 0x2f5;
3507 memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size);
3509 *(ptr + i + 12) = 0x8000800;
3514 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3515 ptr[i++] = 0x104;
3516 ptr[i++] = 0x40aa0055;
3518 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3519 ptr[i++] = 0x1f;
3520 ptr[i++] = 0x2a0055;
3526 static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
3535 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3536 ptr[i++] = 0x207;
3537 ptr[i++] = 0;
3541 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
3542 ptr[i++] = 0x46;
3543 ptr[i++] = 0xffff;
3546 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
3547 ptr[i++] = 0x30000046;
3548 ptr[i++] = 0xffff;
3550 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
3551 ptr[i++] = 0x30000041;
3552 ptr[i++] = 0xffff;
3556 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
3557 ptr[i++] = 0x48;
3558 ptr[i++] = shader_addr >> 8;
3559 ptr[i++] = shader_addr >> 40;
3562 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
3563 ptr[i++] = 0x4a;
3565 ptr[i++] = 0xc0081;
3567 ptr[i++] = 0xc0041;
3569 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
3570 ptr[i++] = 0x4b;
3571 ptr[i++] = 0x18;
3574 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3575 ptr[i++] = 0x1b1;
3576 ptr[i++] = 2;
3579 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3580 ptr[i++] = 0x1c3;
3581 ptr[i++] = 4;
3583 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
3584 ptr[i++] = 0x4c;
3586 ptr[i++] = hang_slow ? 0x45000000 : 0x42000000;
3587 ptr[i++] = hang_slow ? 0x45000000 : 0x42000000;
3589 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
3590 ptr[i++] = 0x50;
3595 ptr[i++] = 0x3f800000;
3596 ptr[i++] = 0x3f800000;
3599 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
3600 ptr[i++] = 0x54;
3606 static int amdgpu_draw_ps_write2hw(uint32_t *ptr,
3641 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
3642 ptr[i++] = 0x7;
3643 ptr[i++] = 0xffff;
3644 ptr[i++] = shader_addr >> 8;
3645 ptr[i++] = shader_addr >> 40;
3650 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
3651 ptr[i++] = 0x8;
3652 ptr[i++] = shader_addr >> 8;
3653 ptr[i++] = shader_addr >> 40;
3656 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
3657 ptr[i++] = 0x30000007;
3658 ptr[i++] = 0xffff;
3660 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
3661 ptr[i++] = 0x30000001;
3662 ptr[i++] = 0xffff;
3666 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
3667 ptr[i++] = sh_registers[j * 2] - 0x2c00;
3668 ptr[i++] = sh_registers[j * 2 + 1];
3673 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3674 ptr[i++] = context_registers[j * 2] - 0xa000;
3675 ptr[i++] = context_registers[j * 2 + 1];
3679 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
3680 ptr[i++] = 0x1b3;
3681 ptr[i++] = 2;
3688 static int amdgpu_draw_draw(uint32_t *ptr, uint32_t version)
3694 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3695 ptr[i++] = 0x40000258;
3696 ptr[i++] = 0xd00ff;
3698 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3699 ptr[i++] = 0x10000242;
3700 ptr[i++] = 0x11;
3703 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3704 ptr[i++] = 0x25b;
3705 ptr[i++] = 0xff;
3707 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3708 ptr[i++] = 0x242;
3709 ptr[i++] = 0x11;
3712 ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
3713 ptr[i++] = 3;
3714 ptr[i++] = 2;