Lines Matching refs:value
50 #define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
124 static int radeon_get_value(int fd, unsigned req, uint32_t *value)
129 *value = 0;
131 info.value = (uintptr_t)value;
477 /* no value to optimize for r6xx/r7xx */
917 /* set some default value to avoid sanity check choking on them */
966 * SAMPLE_SPLIT = tile_split / (bpe * 64), the optimal value is 2
981 * Use recommended value based on tile size for now.
983 * fmask buffer has different optimal value figure them out once we
1319 /* default value */
1346 /* retrieve tiling mode value */
1397 /* retrieve tiling mode value */
1709 /* retrieve tiling mode value */
2147 /* default value */