Lines Matching defs:surf_man
95 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
97 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
137 static int radeon_get_family(struct radeon_surface_manager *surf_man)
139 switch (surf_man->device_id) {
140 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break;
200 static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
206 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
212 surf_man->hw_info.allow_2d = 0;
213 version = drmGetVersion(surf_man->fd);
215 surf_man->hw_info.allow_2d = 1;
221 surf_man->hw_info.num_pipes = 1;
224 surf_man->hw_info.num_pipes = 2;
227 surf_man->hw_info.num_pipes = 4;
230 surf_man->hw_info.num_pipes = 8;
233 surf_man->hw_info.num_pipes = 8;
234 surf_man->hw_info.allow_2d = 0;
240 surf_man->hw_info.num_banks = 4;
243 surf_man->hw_info.num_banks = 8;
246 surf_man->hw_info.num_banks = 8;
247 surf_man->hw_info.allow_2d = 0;
253 surf_man->hw_info.group_bytes = 256;
256 surf_man->hw_info.group_bytes = 512;
259 surf_man->hw_info.group_bytes = 256;
260 surf_man->hw_info.allow_2d = 0;
266 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man,
275 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
300 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
309 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
328 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man,
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
345 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
361 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
371 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
373 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
376 yalign = tilew * surf_man->hw_info.num_pipes;
382 MAX2(surf_man->hw_info.num_pipes *
383 surf_man->hw_info.num_banks *
393 return r6_surface_init_1d(surf_man, surf, offset, i);
404 static int r6_surface_init(struct radeon_surface_manager *surf_man,
434 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
457 r = r6_surface_init_linear(surf_man, surf, 0, 0);
460 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
463 r = r6_surface_init_1d(surf_man, surf, 0, 0);
466 r = r6_surface_init_2d(surf_man, surf, 0, 0);
474 static int r6_surface_best(struct radeon_surface_manager *surf_man,
485 static int eg_init_hw_info(struct radeon_surface_manager *surf_man)
491 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
497 surf_man->hw_info.allow_2d = 0;
498 version = drmGetVersion(surf_man->fd);
500 surf_man->hw_info.allow_2d = 1;
506 surf_man->hw_info.num_pipes = 1;
509 surf_man->hw_info.num_pipes = 2;
512 surf_man->hw_info.num_pipes = 4;
515 surf_man->hw_info.num_pipes = 8;
518 surf_man->hw_info.num_pipes = 8;
519 surf_man->hw_info.allow_2d = 0;
525 surf_man->hw_info.num_banks = 4;
528 surf_man->hw_info.num_banks = 8;
531 surf_man->hw_info.num_banks = 16;
534 surf_man->hw_info.num_banks = 8;
535 surf_man->hw_info.allow_2d = 0;
541 surf_man->hw_info.group_bytes = 256;
544 surf_man->hw_info.group_bytes = 512;
547 surf_man->hw_info.group_bytes = 256;
548 surf_man->hw_info.allow_2d = 0;
554 surf_man->hw_info.row_size = 1024;
557 surf_man->hw_info.row_size = 2048;
560 surf_man->hw_info.row_size = 4096;
563 surf_man->hw_info.row_size = 4096;
564 surf_man->hw_info.allow_2d = 0;
611 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
622 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples);
631 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
652 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
694 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
705 static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
722 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
756 if (surf_man->hw_info.num_banks < surf->mtilea) {
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
788 static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man,
798 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
803 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1,
810 static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
820 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
826 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1,
833 static int eg_surface_init(struct radeon_surface_manager *surf_man,
862 r = eg_surface_sanity(surf_man, surf, mode);
873 r = r6_surface_init_linear(surf_man, surf, 0, 0);
876 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
879 r = eg_surface_init_1d_miptrees(surf_man, surf);
882 r = eg_surface_init_2d_miptrees(surf_man, surf);
908 static int eg_surface_best(struct radeon_surface_manager *surf_man,
921 surf->mtilea = surf_man->hw_info.num_banks;
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
932 r = eg_surface_sanity(surf_man, surf, mode);
974 surf->tile_split = surf_man->hw_info.row_size;
975 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
1013 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
1018 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
1019 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
1199 static int si_init_hw_info(struct radeon_surface_manager *surf_man)
1205 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
1211 surf_man->hw_info.allow_2d = 0;
1212 version = drmGetVersion(surf_man->fd);
1214 if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_array)) {
1215 surf_man->hw_info.allow_2d = 1;
1222 surf_man->hw_info.num_pipes = 1;
1225 surf_man->hw_info.num_pipes = 2;
1228 surf_man->hw_info.num_pipes = 4;
1231 surf_man->hw_info.num_pipes = 8;
1234 surf_man->hw_info.num_pipes = 8;
1235 surf_man->hw_info.allow_2d = 0;
1241 surf_man->hw_info.num_banks = 4;
1244 surf_man->hw_info.num_banks = 8;
1247 surf_man->hw_info.num_banks = 16;
1250 surf_man->hw_info.num_banks = 8;
1251 surf_man->hw_info.allow_2d = 0;
1257 surf_man->hw_info.group_bytes = 256;
1260 surf_man->hw_info.group_bytes = 512;
1263 surf_man->hw_info.group_bytes = 256;
1264 surf_man->hw_info.allow_2d = 0;
1270 surf_man->hw_info.row_size = 1024;
1273 surf_man->hw_info.row_size = 2048;
1276 surf_man->hw_info.row_size = 4096;
1279 surf_man->hw_info.row_size = 4096;
1280 surf_man->hw_info.allow_2d = 0;
1286 static int si_surface_sanity(struct radeon_surface_manager *surf_man,
1304 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
1347 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode];
1398 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
1517 static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
1527 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
1532 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes);
1550 static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
1557 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
1564 slice_align = surf_man->hw_info.group_bytes;
1599 static int si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man,
1605 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1611 r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0);
1617 static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
1681 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1701 static int si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
1710 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1713 r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
1719 r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, surf->stencil_tile_split, surf->bo_size, 0);
1725 static int si_surface_init(struct radeon_surface_manager *surf_man,
1754 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1765 r = r6_surface_init_linear(surf_man, surf, 0, 0);
1768 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
1771 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1774 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1785 static int si_surface_best(struct radeon_surface_manager *surf_man,
1800 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1857 static void cik_get_2d_params(struct radeon_surface_manager *surf_man,
1867 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1945 tile_split = MIN2(surf_man->hw_info.row_size, tile_split);
1953 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index];
2028 static int cik_init_hw_info(struct radeon_surface_manager *surf_man)
2034 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
2040 surf_man->hw_info.allow_2d = 0;
2041 version = drmGetVersion(surf_man->fd);
2043 if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_array) &&
2044 !radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_mode_array)) {
2045 surf_man->hw_info.allow_2d = 1;
2052 surf_man->hw_info.num_pipes = 1;
2055 surf_man->hw_info.num_pipes = 2;
2058 surf_man->hw_info.num_pipes = 4;
2061 surf_man->hw_info.num_pipes = 8;
2064 surf_man->hw_info.num_pipes = 8;
2065 surf_man->hw_info.allow_2d = 0;
2071 surf_man->hw_info.num_banks = 4;
2074 surf_man->hw_info.num_banks = 8;
2077 surf_man->hw_info.num_banks = 16;
2080 surf_man->hw_info.num_banks = 8;
2081 surf_man->hw_info.allow_2d = 0;
2087 surf_man->hw_info.group_bytes = 256;
2090 surf_man->hw_info.group_bytes = 512;
2093 surf_man->hw_info.group_bytes = 256;
2094 surf_man->hw_info.allow_2d = 0;
2100 surf_man->hw_info.row_size = 1024;
2103 surf_man->hw_info.row_size = 2048;
2106 surf_man->hw_info.row_size = 4096;
2109 surf_man->hw_info.row_size = 4096;
2110 surf_man->hw_info.allow_2d = 0;
2116 static int cik_surface_sanity(struct radeon_surface_manager *surf_man,
2132 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
2176 cik_get_2d_params(surf_man, 1, surf->nsamples, false,
2188 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2214 static int cik_surface_init_2d(struct radeon_surface_manager *surf_man,
2234 tile_split = MIN2(surf_man->hw_info.row_size, tile_split);
2283 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2303 static int cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
2310 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2314 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,
2321 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode,
2329 static int cik_surface_init(struct radeon_surface_manager *surf_man,
2358 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2369 r = r6_surface_init_linear(surf_man, surf, 0, 0);
2372 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
2375 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2378 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2389 static int cik_surface_best(struct radeon_surface_manager *surf_man,
2404 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2414 struct radeon_surface_manager *surf_man;
2416 surf_man = calloc(1, sizeof(struct radeon_surface_manager));
2417 if (surf_man == NULL) {
2420 surf_man->fd = fd;
2421 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) {
2424 if (radeon_get_family(surf_man)) {
2428 if (surf_man->family <= CHIP_RV740) {
2429 if (r6_init_hw_info(surf_man)) {
2432 surf_man->surface_init = &r6_surface_init;
2433 surf_man->surface_best = &r6_surface_best;
2434 } else if (surf_man->family <= CHIP_ARUBA) {
2435 if (eg_init_hw_info(surf_man)) {
2438 surf_man->surface_init = &eg_surface_init;
2439 surf_man->surface_best = &eg_surface_best;
2440 } else if (surf_man->family < CHIP_BONAIRE) {
2441 if (si_init_hw_info(surf_man)) {
2444 surf_man->surface_init = &si_surface_init;
2445 surf_man->surface_best = &si_surface_best;
2447 if (cik_init_hw_info(surf_man)) {
2450 surf_man->surface_init = &cik_surface_init;
2451 surf_man->surface_best = &cik_surface_best;
2454 return surf_man;
2456 free(surf_man);
2461 radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
2463 free(surf_man);
2466 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
2471 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) {
2514 if (surf_man->family >= CHIP_RV770) {
2535 radeon_surface_init(struct radeon_surface_manager *surf_man,
2544 r = radeon_surface_sanity(surf_man, surf, type, mode);
2548 return surf_man->surface_init(surf_man, surf);
2552 radeon_surface_best(struct radeon_surface_manager *surf_man,
2561 r = radeon_surface_sanity(surf_man, surf, type, mode);
2565 return surf_man->surface_best(surf_man, surf);