Lines Matching defs:level
157 static unsigned mip_minify(unsigned size, unsigned level)
161 val = MAX2(1, size >> level);
162 if (level > 0)
169 unsigned bpe, unsigned level,
173 surflevel->npix_x = mip_minify(surf->npix_x, level);
174 surflevel->npix_y = mip_minify(surf->npix_y, level);
175 surflevel->npix_z = mip_minify(surf->npix_z, level);
289 surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
317 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
350 surf->level[i].mode = RADEON_SURF_MODE_1D;
351 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
390 surf->level[i].mode = RADEON_SURF_MODE_2D;
391 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
392 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
573 unsigned level,
582 surflevel->npix_x = mip_minify(surf->npix_x, level);
583 surflevel->npix_y = mip_minify(surf->npix_y, level);
584 surflevel->npix_z = mip_minify(surf->npix_z, level);
613 struct radeon_surface_level *level,
641 level[i].mode = RADEON_SURF_MODE_1D;
642 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
654 struct radeon_surface_level *level,
691 level[i].mode = RADEON_SURF_MODE_2D;
692 eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset);
693 if (level[i].mode == RADEON_SURF_MODE_1D) {
694 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
798 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
820 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
1423 unsigned bpe, unsigned level,
1427 if (level == 0) {
1430 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
1432 surflevel->npix_y = mip_minify(surf->npix_y, level);
1433 surflevel->npix_z = mip_minify(surf->npix_z, level);
1435 if (level == 0 && surf->last_level > 0) {
1450 if (level == 0 && surf->last_level == 0)
1471 unsigned bpe, unsigned level, unsigned slice_pt,
1477 if (level == 0) {
1480 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
1482 surflevel->npix_y = mip_minify(surf->npix_y, level);
1483 surflevel->npix_z = mip_minify(surf->npix_z, level);
1485 if (level == 0 && surf->last_level > 0) {
1536 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1537 si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset);
1552 struct radeon_surface_level *level,
1579 level[i].mode = RADEON_SURF_MODE_1D;
1580 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset);
1587 if (surf->level == level) {
1605 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1619 struct radeon_surface_level *level,
1661 level[i].mode = RADEON_SURF_MODE_2D;
1662 si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
1663 if (level[i].mode == RADEON_SURF_MODE_1D) {
1681 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1689 if (surf->level == level) {
1713 r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
2216 struct radeon_surface_level *level,
2263 level[i].mode = RADEON_SURF_MODE_2D;
2264 si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
2265 if (level[i].mode == RADEON_SURF_MODE_1D) {
2283 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2291 if (surf->level == level) {
2314 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,