Lines Matching refs:__u64
146 __u64 bo_size;
148 __u64 alignment;
150 __u64 domains;
152 __u64 domain_flags;
183 __u64 bo_info_ptr;
269 __u64 flags;
299 __u64 flags;
335 __u64 addr;
336 __u64 size;
378 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
380 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
393 __u64 flags;
395 __u64 tiling_info;
409 __u64 addr_ptr;
423 __u64 timeout;
443 __u64 handle;
445 __u64 timeout;
454 __u64 status;
467 __u64 seq_no;
472 __u64 fences;
475 __u64 timeout_ns;
498 __u64 value;
542 __u64 va_address;
544 __u64 offset_in_bo;
546 __u64 map_size;
575 __u64 chunk_data;
585 /** this points to __u64 * which point to cs chunks */
586 __u64 chunks;
590 __u64 handle;
631 __u64 va_start;
647 __u64 handle;
662 __u64 point;
863 __u64 return_pointer;
931 __u64 vram_size;
932 __u64 vram_cpu_accessible_size;
933 __u64 gtt_size;
938 __u64 total_heap_size;
941 __u64 usable_heap_size;
949 __u64 heap_usage;
955 __u64 max_allocation;
1003 __u64 max_engine_clock;
1004 __u64 max_memory_clock;
1015 __u64 ids_flags;
1017 __u64 virtual_address_offset;
1019 __u64 virtual_address_max;
1036 __u64 prim_buf_gpu_addr;
1038 __u64 pos_buf_gpu_addr;
1040 __u64 cntl_sb_buf_gpu_addr;
1042 __u64 param_buf_gpu_addr;
1065 __u64 high_va_offset;
1067 __u64 high_va_max;
1071 __u64 tcc_disabled_mask;
1079 __u64 capabilities_flags;