Lines Matching refs:info
99 struct drm_amdgpu_info_hw_ip *info)
104 request.return_pointer = (uintptr_t)info;
105 request.return_size = sizeof(*info);
149 dev->info.asic_id = dev->dev_info.device_id;
150 dev->info.chip_rev = dev->dev_info.chip_rev;
151 dev->info.chip_external_rev = dev->dev_info.external_rev;
152 dev->info.family_id = dev->dev_info.family;
153 dev->info.max_engine_clk = dev->dev_info.max_engine_clock;
154 dev->info.max_memory_clk = dev->dev_info.max_memory_clock;
155 dev->info.gpu_counter_freq = dev->dev_info.gpu_counter_freq;
156 dev->info.enabled_rb_pipes_mask = dev->dev_info.enabled_rb_pipes_mask;
157 dev->info.rb_pipes = dev->dev_info.num_rb_pipes;
158 dev->info.ids_flags = dev->dev_info.ids_flags;
159 dev->info.num_hw_gfx_contexts = dev->dev_info.num_hw_gfx_contexts;
160 dev->info.num_shader_engines = dev->dev_info.num_shader_engines;
161 dev->info.num_shader_arrays_per_engine =
163 dev->info.vram_type = dev->dev_info.vram_type;
164 dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
165 dev->info.ce_ram_size = dev->dev_info.ce_ram_size;
166 dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config;
167 dev->info.pci_rev_id = dev->dev_info.pci_rev;
169 if (dev->info.family_id < AMDGPU_FAMILY_AI) {
170 for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
176 &dev->info.backend_disable[i]);
180 dev->info.backend_disable[i] =
181 (dev->info.backend_disable[i] >> 16) & 0xff;
184 &dev->info.pa_sc_raster_cfg[i]);
188 if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
190 &dev->info.pa_sc_raster_cfg1[i]);
198 &dev->info.gb_addr_cfg);
202 if (dev->info.family_id < AMDGPU_FAMILY_AI) {
204 dev->info.gb_tile_mode);
208 if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
210 dev->info.gb_macro_tile_mode);
216 &dev->info.mc_arb_ramcfg);
221 dev->info.cu_active_number = dev->dev_info.cu_active_number;
222 dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
223 memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
225 /* TODO: info->max_quad_shader_pipes is not set */
226 /* TODO: info->avail_quad_shader_pipes is not set */
227 /* TODO: info->cache_entries_per_quad_pipe is not set */
232 struct amdgpu_gpu_info *info)
234 if (!dev || !info)
237 /* Get ASIC info*/
238 *info = dev->info;
246 struct amdgpu_heap_info *info)
261 info->heap_size = vram_gtt_info.vram_cpu_accessible_size;
263 info->heap_size = vram_gtt_info.vram_size;
265 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
269 sizeof(info->heap_usage),
270 &info->heap_usage);
273 sizeof(info->heap_usage),
274 &info->heap_usage);
279 info->heap_size = vram_gtt_info.gtt_size;
280 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
283 sizeof(info->heap_usage),
284 &info->heap_usage);