Lines Matching refs:args
56 union drm_amdgpu_ctx args;
74 memset(&args, 0, sizeof(args));
75 args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
76 args.in.priority = priority;
78 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
82 gpu_context->id = args.out.alloc.ctx_id;
113 union drm_amdgpu_ctx args;
123 memset(&args, 0, sizeof(args));
124 args.in.op = AMDGPU_CTX_OP_FREE_CTX;
125 args.in.ctx_id = context->id;
127 &args, sizeof(args));
150 union drm_amdgpu_sched args;
156 memset(&args, 0, sizeof(args));
158 args.in.op = AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE;
159 args.in.fd = dev->fd;
160 args.in.priority = priority;
161 args.in.ctx_id = context->id;
163 r = drmCommandWrite(master_fd, DRM_AMDGPU_SCHED, &args, sizeof(args));
175 union drm_amdgpu_ctx args;
181 memset(&args, 0, sizeof(args));
182 args.in.op = op;
183 args.in.ctx_id = context->id;
184 args.in.flags = flags;
186 &args, sizeof(args));
188 *out_flags = args.out.pstate.flags;
195 union drm_amdgpu_ctx args;
201 memset(&args, 0, sizeof(args));
202 args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
203 args.in.ctx_id = context->id;
205 &args, sizeof(args));
207 *state = args.out.state.reset_status;
208 *hangs = args.out.state.hangs;
216 union drm_amdgpu_ctx args;
222 memset(&args, 0, sizeof(args));
223 args.in.op = AMDGPU_CTX_OP_QUERY_STATE2;
224 args.in.ctx_id = context->id;
226 &args, sizeof(args));
228 *flags = args.out.state.flags;
444 union drm_amdgpu_wait_cs args;
447 memset(&args, 0, sizeof(args));
448 args.in.handle = handle;
449 args.in.ip_type = ip;
450 args.in.ip_instance = ip_instance;
451 args.in.ring = ring;
452 args.in.ctx_id = context->id;
455 args.in.timeout = timeout_ns;
457 args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
459 r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
463 *busy = args.out.status;
507 union drm_amdgpu_wait_fences args;
520 memset(&args, 0, sizeof(args));
521 args.in.fences = (uint64_t)(uintptr_t)drm_fences;
522 args.in.fence_count = fence_count;
523 args.in.wait_all = wait_all;
524 args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns);
526 r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args);
530 *status = args.out.status;
533 *first = args.out.first_signaled;