Lines Matching refs:resultId
111 void disassembleInstruction(Id resultId, Id typeId, Op opCode, int numOperands);
194 Id resultId = 0;
196 resultId = stream[word++];
200 idInstruction[resultId] = instructionStart;
203 outputResultId(resultId);
208 disassembleInstruction(resultId, typeId, opCode, numOperands);
340 void SpirvStream::disassembleInstruction(Id resultId, Id /*typeId*/, Op opCode, int numOperands)
354 idDescriptor[resultId] = decodeString().second;
357 if (resultId != 0 && idDescriptor[resultId].size() == 0) {
361 case 8: idDescriptor[resultId] = "int8_t"; break;
362 case 16: idDescriptor[resultId] = "int16_t"; break;
364 case 32: idDescriptor[resultId] = "int"; break;
365 case 64: idDescriptor[resultId] = "int64_t"; break;
370 case 16: idDescriptor[resultId] = "float16_t"; break;
372 case 32: idDescriptor[resultId] = "float"; break;
373 case 64: idDescriptor[resultId] = "float64_t"; break;
377 idDescriptor[resultId] = "bool";
380 idDescriptor[resultId] = "struct";
383 idDescriptor[resultId] = "ptr";
387 idDescriptor[resultId].append(idDescriptor[stream[word]].begin(), idDescriptor[stream[word]].begin() + 1);
389 idDescriptor[resultId].append("8");
392 idDescriptor[resultId].append("16");
395 idDescriptor[resultId].append("64");
398 idDescriptor[resultId].append("vec");
400 case 2: idDescriptor[resultId].append("2"); break;
401 case 3: idDescriptor[resultId].append("3"); break;
402 case 4: idDescriptor[resultId].append("4"); break;
403 case 8: idDescriptor[resultId].append("8"); break;
404 case 16: idDescriptor[resultId].append("16"); break;
405 case 32: idDescriptor[resultId].append("32"); break;